Semiconductor device and electronic device
View Patent ↗A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to a second wiring,
wherein the other of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fifth transistor are electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor are electrically connected to at least one of a gate of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor and the gate of the fifth transistor,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor and the gate of the fifth transistor,
wherein a gate of the seventh transistor is electrically connected to a sixth wiring,
wherein a W/L of the first transistor, where W is a channel width and L is a channel length, is higher than W/Ls of the second to seventh transistors,
wherein the first wiring is configured to transmit a first clock signal, and
wherein the second wiring is configured to transmit an output signal.
2. The semiconductor device according to claim 1 , wherein the first wiring is configured to transmit a first clock signal.
3. The semiconductor device according to claim 1 , wherein the second wiring is configured to transmit an output signal.
4. The semiconductor device according to claim 1 , wherein the first to seventh transistors have the same polarity.
5. The semiconductor device according to claim 1 , wherein a channel formation region of each of the first to fifth transistors comprises an oxide semiconductor.
6. The semiconductor device according to claim 1 , further comprising a first capacitor,
wherein one electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor, and
wherein the other electrode of the first capacitor is electrically connected to the gate of the first transistor.
7. The semiconductor device according to claim 1 , further comprising a second capacitor,
wherein one electrode of the second capacitor is electrically connected to the other of the source and the drain of the fourth transistor, and
wherein the other electrode of the second capacitor is electrically connected to a gate of the fourth transistor.
8. The semiconductor device according to claim 1 , wherein each of the first to fifth transistors comprises a back gate.
9. A display module comprising:
the semiconductor device according to claim 1 ; and
an FPC.
10. An electronic device comprising:
the display module according to claim 9 ; and
a speaker, an operation button, and/or an antenna.
11. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor and one of a source and a drain of the second transistor are electrically connected to a second wiring,
wherein the other of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fifth transistor are electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor are electrically connected to at least one of a gate of the second transistor and a gate of the third transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor and the gate of the fifth transistor,
wherein a gate of the sixth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the first transistor and the gate of the fifth transistor,
wherein a gate of the seventh transistor is electrically connected to a sixth wiring, and
wherein a W/L of the first transistor, where W is a channel width and L is a channel length, is higher than W/Ls of the second to seventh transistors.
12. The semiconductor device according to claim 11 ,
wherein the first wiring is configured to transmit a first clock signal, and
wherein the second wiring is configured to transmit an output signal.
13. The semiconductor device according to claim 11 , wherein the first to seventh transistors have the same polarity.
14. The semiconductor device according to claim 11 , wherein a channel formation region of each of the first to fifth transistors comprises an oxide semiconductor.
15. The semiconductor device according to claim 11 , further comprising a first capacitor,
wherein one electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor, and
wherein the other electrode of the first capacitor is electrically connected to the gate of the first transistor.
16. The semiconductor device according to claim 11 , further comprising a second capacitor,
wherein one electrode of the second capacitor is electrically connected to the other of the source and the drain of the fourth transistor, and
wherein the other electrode of the second capacitor is electrically connected to a gate of the fourth transistor.
17. The semiconductor device according to claim 11 , wherein each of the first to fifth transistors comprises a back gate.
18. A display module comprising:
the semiconductor device according to claim 11 ; and
an FPC.
19. An electronic device comprising:
the display module according to claim 18 ; and
a speaker, an operation button, and/or an antenna.
20. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the seventh transistor is electrically connected to a seventh wiring.
21. The semiconductor device according to claim 12 , wherein the other of the source and the drain of the seventh transistor is electrically connected to a seventh wiring.