Microelectronics package with an integrated heat spreader having indentations
Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.
1. A microelectronics package comprising:
a first die;
a second die;
a third die; and
an integrated heat spreader, the integrated heat spreader including a first surface, the first surface defining:
a first indentation located in between the first die and the second die, and
a second indentation located in between the third die and the first die and the second die.
2. The microelectronics package of claim 1 , further comprising a filler located within the first indentation.
3. The microelectronics package of claim 2 , wherein the filler has a thermal conductivity at least one order of magnitude less than a thermal conductivity of the integrated heat spreader.
4. The microelectronics package of claim 1 , wherein the first indentation at least partially surrounds the first die or the second die.
5. The microelectronics package of claim 1 , wherein the integrate heat spreader has a thickness and the first indentation has a depth of about 80% to about 95% of the thickness.
6. The microelectronics package of claim 1 , wherein the first die has a first power density and the second die has a second power density, the first power density being at least one order of magnitude less than the second power density.
7. The microelectronics package of claim 1 , wherein the first indentation and the second indentation each has a similar profile.
8. The microelectronics package of claim 1 , further comprising a heat sink attached to a second surface of the integrated heat spreader.
9. The microelectronics package of claim 1 , wherein the first indentation thermally isolates the first die from the second die.
10. The microelectronics package of claim 1 , wherein the first indentation has a non-uniform profile.
11. The microelectronics package of claim 1 , wherein the first die is a primary die and the second die is a high bandwidth memory die.
12. The microelectronics package of claim 1 , wherein the first indentation and the second indentation each has a different profile.
13. A method of manufacturing a microelectronics package, the method comprising:
attaching a first die, a second die, and a third die to a substrate;
forming a first indentation in a first surface of an integrated heat spreader;
forming a second indentation in the integrated heat spreader; and
attaching the integrated heat spreader to the first die, the second die, and the third die such that:
the first indentation is located in between the first die and the second die, and
the second indentation is located in between the third die and the first die and the second die.
14. The method of claim 13 , further comprising applying a filler within the first indentation.
15. The method of claim 13 , wherein forming the first indentation includes forming the first indentation such that when the integrated heat spreader is attached to the first die and the second die, the first indentation at least partially surrounds the first die or the second die.
16. The method of claim 13 , further comprising attaching a heat sink to a second surface of the integrated heat spreader.
17. A microelectronics package comprising: a first die; a second die; a third die; and an integrated heat spreader, the integrated heat spreader including a first surface, the first surface defining:
a first indentation located in between the first die and the second die, a second indentation located in between the first die and the third die, and a third indentation located in between the second die and the third die.
18. The microelectronics package of claim 17 , wherein the first indentation and the second indentation each has a similar profile.
19. The microelectronics package of claim 17 , wherein the first indentation at least partially surrounds the first die or the second die.
20. The microelectronics package of claim 17 , wherein the first indentation has a non-uniform profile.
21. The microelectronics package of claim 17 , wherein the first die is a primary die and the second die is a high bandwidth memory die.
22. The microelectronics package of claim 17 , wherein the first indentation and the second indentation each has a different profile.
23. A method of manufacturing a microelectronics package, the method comprising:
attaching a first die, a second die, and a third die to a substrate; forming a first indentation in a first surface of an integrated heat spreader; forming a second indentation and a third indentation in the integrated heat spreader; and attaching the integrated heat spreader to the first die, the second die, and the third die such that:
the first indentation is located in between the first die and the second die, the second indentation is located in between the first die and the third die, and the third indentation is located in between the second die and the third die.
24. The method of claim 23 , further comprising applying a filler within the first indentation.
25. The method of claim 23 , wherein forming the first indentation includes forming the first indentation such that when the integrated heat spreader is attached to the first die and the second die, the first indentation at least partially surrounds the first die or the second die.