Multi-stacked package-on-package structures
A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
1. A device comprising:
a first substrate;
a first integrated circuit die over the first substrate;
a second integrated circuit die over the first substrate, the second integrated circuit die having a different function than the first integrated circuit die;
a passive device over the second integrated circuit die, the passive device comprising a second substrate and through silicon vias (TSVs) extending through the second substrate; and
a first redistribution structure over the passive device, the first integrated circuit die, and the second integrated circuit die, the TSVs of the passive device electrically connecting the second integrated circuit die to the first redistribution structure.
2. The device of claim 1 further comprising:
a second redistribution structure disposed between the passive device and the second integrated circuit die, the TSVs of the passive device electrically connecting the second redistribution structure to the first redistribution structure.
3. The device of claim 2 further comprising:
a first encapsulant around the passive device, the first encapsulant being disposed between the first redistribution structure and the second redistribution structure.
4. The device of claim 3 further comprising:
a second encapsulant around the first integrated circuit die and the second integrated circuit die, the second encapsulant being disposed between the second redistribution structure and the first substrate.
5. The device of claim 3 further comprising:
conductive vias extending through the first encapsulant, the conductive vias electrically connecting the second redistribution structure to the first redistribution structure.
6. The device of claim 5 , wherein top surfaces of the second encapsulant, the first integrated circuit die, and the second integrated circuit die are level, and wherein top surfaces of the conductive vias, the first encapsulant, and the passive device are level.
7. The device of claim 2 , wherein the passive device is physically and electrically connected to the second redistribution structure with solder connections.
8. The device of claim 1 , wherein the first integrated circuit die is a high-bandwidth memory (HBM) device, the second integrated circuit die is a system-on-chip (SoC) device, and the passive device is an integrated voltage regulator (IVR).
9. A device comprising:
a first substrate;
a first integrated circuit die over the first substrate;
a second integrated circuit die over the first substrate, the second integrated circuit die having a different function than the first integrated circuit die;
a first encapsulant around the first integrated circuit die and the second integrated circuit die;
a passive device over the first encapsulant, the passive device comprising a second substrate and through silicon vias (TSVs) extending through the second substrate, the TSVs being electrically connected to the second integrated circuit die; and
conductive vias surrounding the passive device, the conductive vias being electrically connected to the first integrated circuit die and the second integrated circuit die.
10. The device of claim 9 further comprising:
a second encapsulant around the passive device and the conductive vias.
11. The device of claim 10 further comprising:
a first redistribution structure disposed between the first encapsulant and the second encapsulant, the first integrated circuit die and the second integrated circuit die being physically and electrically connected to a first side of the first redistribution structure.
12. The device of claim 11 , wherein the passive device is physically and electrically connected to a second side of the first redistribution structure with solder connections.
13. The device of claim 11 further comprising:
a second redistribution structure over the second encapsulant, the second redistribution structure being physically and electrically connected to the conductive vias and the TSVs of the passive device.
14. The device of claim 9 , wherein the first integrated circuit die is a high-bandwidth memory (HBM) device, the second integrated circuit die is a system-on-chip (SoC) device, and the passive device is an integrated voltage regulator (IVR).
15. A device comprising:
a first substrate;
a first integrated circuit die over the first substrate;
a second integrated circuit die over the first substrate, the second integrated circuit die having a different function than the first integrated circuit die;
a first encapsulant disposed over the first integrated circuit die and the second integrated circuit die;
a passive device disposed in the first encapsulant, the passive device comprising a second substrate and through silicon vias (TSVs) extending through the second substrate; and
a first redistribution structure over the passive device and the first encapsulant, the TSVs of the passive device electrically connecting the second integrated circuit die to the first redistribution structure.
16. The device of claim 15 further comprising:
conductive vias extending through the first encapsulant, the conductive vias being physically and electrically connected to the first redistribution structure.
17. The device of claim 16 further comprising:
a second redistribution structure disposed between the passive device and the second integrated circuit die, the conductive vias and the TSVs of the passive device electrically connecting the second redistribution structure to the first redistribution structure.
18. The device of claim 17 , wherein the passive device is physically and electrically connected to the second redistribution structure with solder connections.
19. The device of claim 17 further comprising:
a second encapsulant around the first integrated circuit die and the second integrated circuit die, the second redistribution structure separating the first encapsulant from the second encapsulant.
20. The device of claim 15 , wherein the first integrated circuit die is a high-bandwidth memory (HBM) device, the second integrated circuit die is a system-on-chip (SoC) device, and the passive device is an integrated voltage regulator (IVR).