Threshold voltage control using channel digital etch
View Patent ↗A method is presented for fine-tuning a threshold voltage of a nanosheet structure. The method includes forming a nanosheet stack over a substrate including a plurality of sacrificial layers and a plurality of nanowires, forming a sacrificial gate structure over the nanosheet stack, and partially etching one or more sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers. The method includes removing the sacrificial gate structure, removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires, forming an oxidation channel on the exposed surface on only either a top side or bottom side of each of the plurality of nanowires, removing the oxidation channels to form a recess on each of the plurality of nanowires, and depositing a high-k metal gate extending into the recess of each of the plurality of nanowires.
1. A method for fine-tuning a threshold voltage of a nanosheet structure, the method comprising:
forming a nanosheet stack including a plurality of sacrificial layers and a plurality of nanowires;
forming a sacrificial gate structure over the nanosheet stack;
partially etching one or more of the plurality of sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers;
removing the sacrificial gate structure;
removing at least one of the remaining sections of sacrificial layers to expose a surface of each of the plurality of nanowires;
forming an oxidation channel directly contacting the exposed surface of each of the plurality of nanowires on only either a top side or a bottom side of each of the plurality of nanowires; and
removing the oxidation channels to form a recess on each of the plurality of nanowires.
2. The method of claim 1 , further comprising forming first spacers adjacent the sacrificial gate structure.
3. The method of claim 2 , further comprising filling the cavities with second spacers.
4. The method of claim 3 , further comprising forming source/drain regions adjacent the nanosheet stack.
5. The method of claim 4 , wherein the removing of the at least one of the remaining sections of sacrificial layers results in gaps formed between the plurality of nanowires.
6. The method of claim 5 , further comprising depositing a high-k metal gate (HKMG) extending into the recess of each of the plurality of nanowires and filling the gaps with the HKMG.
7. The method of claim 1 , wherein the plurality of sacrificial layers are three or more layers.
8. The method of claim 7 , wherein the first layer is a SiGe alloy layer having about 50% atomic concentration of Ge, the second layer is a SiGe alloy layer having about 15% atomic concentration of Ge, and the third layer is a SiGe alloy layer having about 25% atomic concentration of Ge.
9. The method of claim 8 , wherein the plurality of nanowires are Si nanowires.
10. The method of claim 9 , wherein the one or more of the plurality of sacrificial layers partially etched are the second SiGe alloy layer having about 15% atomic concentration of Ge and the third SiGe alloy layer having about 25% atomic concentration of Ge.
11. A method for fine-tuning a threshold voltage of a nanosheet structure, the method comprising:
forming a nanosheet stack including a plurality of sacrificial layers and a plurality of nanowires;
forming first spacers adjacent a sacrificial gate structure formed over the nanosheet stack;
partially etching one or more of the plurality of sacrificial layers to form cavities, the partial etching resulting in remaining sections of sacrificial layers;
filling the cavities with second spacers;
forming source/drain regions adjacent the nanosheet stack;
removing the sacrificial gate structure;
removing at least one of the remaining sections of sacrificial layers to form gaps between the plurality of nanowires; and
forming oxidation channels directly contacting each of the plurality of nanowires on only one side of each of the plurality of nanowires.
12. The method of claim 11 , further comprising:
removing at least another of the remaining sections of sacrificial layers along with the oxidation channels formed on each of the plurality of nanowires;
depositing a high-k metal gate (HKMG) between the first spacers and within the gaps formed between the plurality of nanowires; and
extending the HKMG into recesses formed on the plurality of nanowires from the removal of the oxidation channels.
13. The method of claim 11 , wherein the plurality of sacrificial layers are three or more layers.
14. The method of claim 13 , wherein the first layer is a silicon germanium (SiGe) alloy layer having about 50% atomic concentration of Ge, the second layer is a SiGe alloy layer having about 15% atomic concentration of Ge, and the third layer is a SiGe alloy layer having about 25% atomic concentration of Ge.
15. The method of claim 14 , wherein the plurality of nanowires are silicon (Si) nanowires.
16. The method of claim 15 , wherein the one or more of the plurality of sacrificial layers partially etched are the second SiGe alloy layer having about 15% atomic concentration of Ge and the third SiGe alloy layer having about 25% atomic concentration of Ge.