Semiconductor apparatus, degradation value determination system and processing system
A semiconductor apparatus includes an operation oscillator, a reference oscillator, a first operation switch connected in series with the operation oscillator between a power supply potential VDD and a ground potential GND, a first reference switch connected in series with the reference oscillator between the power supply potential VDD and the ground potential GND, a second reference switch connected in parallel with the reference oscillator between the power supply potential VDD and the ground potential GND, an operation counter configured to count the number of output pulses from the operation oscillator in a measurement period, and a reference counter configured to count the number of output pulses from the reference oscillator in the measurement period.
1. A semiconductor apparatus comprising:
an operation oscillator;
a reference oscillator;
a first operation switch connected in series with the operation oscillator between a power supply potential and a ground potential;
a first reference switch connected in series with the reference oscillator between the power supply potential and the ground potential;
a second reference switch connected in parallel with the reference oscillator between the power supply potential and the ground potential;
an operation counter configured to count a number of first output pulses from the operation oscillator in a predetermined measurement period;
a reference counter configured to count a number of second output pulses from the reference oscillator in the predetermined measurement period;
a first gating component inputs the number of first output pulses; and
a second gating component inputs the number of second output pulses,
wherein the predetermined measurement period is set as a period during which the first gating component and the second gating component are in a through state.
2. The semiconductor apparatus according to claim 1 , further comprising a second operation switch connected in parallel with the operation oscillator between the power supply potential and the ground potential.
3. The semiconductor apparatus according to claim 2 , further comprising a switch control circuit configured to control the first reference switch, the first operation switch, the second reference switch, and the second operation switch, wherein
the switch control circuit turns off the first reference switch, turns on the first operation switch, turns on the second reference switch, and turns off the second operation switch in a normal operating state, and
the switch control circuit turns on the first reference switch, turns on the first operation switch, turns off the second reference switch, and turns off the second operation switch in a degradation level measurement state.
4. The semiconductor apparatus according to claim 2 , wherein
the first reference switch and the first operation switch are PMOS transistors, and
the second reference switch and the second operation switch are NMOS transistors.
5. The semiconductor apparatus according to claim 2 , wherein
the first reference switch and the first operation switch are NMOS transistors, and
the second reference switch and the second operation switch are PMOS transistors.
6. The semiconductor apparatus according to claim 2 , further comprising:
an operation current source connected in series with the second operation switch; and
a reference current source connected in series with the second reference switch.
7. The semiconductor apparatus according to claim 1 , further comprising a regulator connected to the power supply potential.
8. A degradation value determination system comprising:
a plurality of sensor circuits; and
a sensor control circuit configured to control the sensor circuit, wherein
each of the plurality of sensor circuits comprises a semiconductor apparatus according to claim 1 , and
the sensor control circuit determines a degradation level of an object to be measured according to a result of a comparison between counter values of the operation counter and the reference counter.
9. The degradation value determination system according to claim 8 , wherein the sensor control circuit corrects an operating voltage of the object to be measured according to the degradation level of the operation oscillator of the plurality of sensor circuits.
10. A processing system comprising:
a plurality of macro blocks; and
a plurality of sensor circuits provided so as to correspond to the plurality of macro blocks, wherein
each of the plurality of sensor circuits comprises a semiconductor apparatus according to claim 1 , and
the sensor circuits are connected to power sources from which power is supplied to corresponding macro blocks.
11. The processing system according to claim 10 , further comprising:
a sensor control unit configured to determine a degradation level of the operation oscillator according to a result of a comparison between counter values of the operation counter and the reference counter; and
a system controller configured to assign weights for assigning a task to the plurality of macro blocks.
12. The processing system according to claim 10 , further comprising:
a temperature sensor configured to measure an environment temperature of the macro block;
a sensor control unit configured to determine a degradation level of the operation oscillator according to a result of a comparison between counter values of the operation counter and the reference counter; and
a system controller configured to determine a number of operating macro blocks according to the environment temperature, wherein
the system controller preferentially stops an operation of a macro block having a high degradation level.
13. The processing system according to claim 10 , further comprising:
a sensor control unit configured to determine a degradation level of an object to be measured according to a result of a comparison between counter values of the operation counter and the reference counter; and
a system controller configured to individually set each of power supply voltages of the plurality of macro blocks according to degradation level.
14. The processing system according to claim 10 , wherein the macro blocks are processor cores.