PLL circuit

1. A PLL circuit comprising:

a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;

a variable frequency divider to perform frequency dividing on an output signal of the voltage-controlled oscillator at a supplied frequency dividing ratio;

a phase frequency comparator to compare an output signal of the variable frequency divider with a reference signal;

a charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;

a loop filter to supply a signal obtained by smoothing the output signal of the charge pump to the voltage-controlled oscillator;

a ΔΣ modulator to generate the frequency dividing ratio for the variable frequency divider depending on a supplied signal;

a first frequency accumulator to operate using the output signal of the variable frequency divider as a clock, and generate an output value corresponding to the clock as an input value for the ΔΣ modulator;

a second frequency accumulator to operate using the reference signal as a clock, and generate an output value corresponding to the clock;

a comparison operating circuit to compare the output values of the first frequency accumulator and the second frequency accumulator, and calculate a parameter so that a result of the comparison falls within a set value; and

a digital-analog converting circuit to output a signal to be added to an output of the loop filter depending on the parameter output from the comparison operating circuit.

2. The PLL circuit according to claim 1 , wherein

the second frequency accumulator of claim 1 is replaced with both a first counter that operates using the output signal of the variable frequency divider as a clock and outputs a count value corresponding to the clock, and a second counter that operates using the reference signal as a clock and outputs a count value corresponding to the clock, and

the comparison operating circuit of claim 1 is replaced with a comparison operating circuit that calculates the parameter so that a difference between the count values of the first counter and the second counter falls within a set value.

3. The PLL circuit according to claim 1 , further comprising

a frequency divider to perform frequency dividing on the output signal of the voltage-controlled oscillator,

wherein

the second frequency accumulator of claim 1 is replaced with both a first counter that operates using an output signal of the frequency divider as a clock and outputs a count value corresponding to the clock, and a second counter that operates using the reference signal as a clock and outputs a count value corresponding to the clock, and

the comparison operating circuit of claim 1 is replaced with a comparison operating circuit that calculates the parameter so that a difference between the count values of the first counter and the second counter falls within a set value.

4. A PLL circuit comprising:

a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;

a variable frequency divider to perform frequency dividing on an output signal of the voltage-controlled oscillator at a supplied frequency dividing ratio;

a phase frequency comparator to compare an output signal of the variable frequency divider with a reference signal;

a charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator, the charge pump being capable of changing the output depending on a supplied parameter;

a loop filter to supply a signal obtained by smoothing the output signal of the charge pump to the voltage-controlled oscillator;

a ΔΣ modulator to generate the frequency dividing ratio for the variable frequency divider depending on a supplied signal;

a first frequency accumulator to operate using the output signal of the variable frequency divider as a clock, and generate an output value corresponding to the clock as an input value for the ΔΣ modulator;

a second frequency accumulator to operate using the reference signal as a clock, and generate an output value corresponding to the clock; and

a comparison operating circuit to compare the output values of the first frequency accumulator and the second frequency accumulator, and calculate the parameter for the charge pump so that a result of the comparison falls within a set value.

5. A PLL circuit comprising:

a voltage-controlled oscillator to transmit a frequency signal corresponding to a voltage of a supplied signal;

a variable frequency divider to perform frequency dividing on an output signal of the voltage-controlled oscillator at a supplied frequency dividing ratio;

a phase frequency comparator to compare an output signal of the variable frequency divider with a reference signal;

a charge pump to output a signal corresponding to a result of the comparison performed by the phase frequency comparator;

a loop filter to supply a signal obtained by smoothing the output signal of the charge pump to the voltage-controlled oscillator, the loop filter being capable of changing a frequency band to be filtered depending on a supplied parameter;

a ΔΣ modulator to generate the frequency dividing ratio for the variable frequency divider depending on a supplied signal;

a first frequency accumulator to operate using the output signal of the variable frequency divider as a clock, and generate an output value corresponding to the clock as an input value for the ΔΣ modulator;

a second frequency accumulator to operate using the reference signal as a clock, and generate an output value corresponding to the clock; and

a comparison operating circuit to compare the output values of the first frequency accumulator and the second frequency accumulator, and calculate the parameter for the loop filter so that a result of the comparison falls within a set value.