Pipelined SAR with TDC converter

1. An analog-to-digital converter (ADC), comprising:

a successive approximation register configured to receive an input signal and to generate a first digital signal and a residue voltage;

a voltage-to-time conversion element configured to convert the residue voltage to a time domain representation, the voltage-to-time conversion element comprising:

an amplifier comprising an input coupled to an output of the successive approximation register;

a zero crossing detector directly coupled to an output of the amplifier; and

a time-to-digital converter coupled to an output of the zero crossing detector and configured to generate a second digital signal.

2. The ADC of claim 1 , wherein the successive approximation register comprises:

an arithmetic unit having a first input and a second input;

a comparator coupled to an output of the arithmetic unit;

a successive approximation register (SAR) logic unit coupled to an output of the comparator;

a capacitive digital-to-analog converter (CDAC) coupled to an output of the SAR logic unit and to the first input of the arithmetic unit; and

a track-and-hold circuit having an input configured to receive the input signal and an output coupled to the second input of the arithmetic unit.

3. The ADC of claim 2 ,

wherein the track-and-hold circuit is configured to provide a voltage to the second input of the arithmetic unit, the voltage having a value that corresponds to a value of the input signal at a first time; and

wherein the arithmetic unit is configured to generate the residue voltage based upon the voltage and a signal output from the CDAC.

4. The ADC of claim 2 ,

wherein the CDAC comprises a plurality of capacitors; and

wherein the time domain representation is proportional to a sum of capacitances of the plurality of capacitors.

5. The ADC of claim 1 , wherein the zero crossing detector comprises a comparator configured to generate the time domain representation by comparing a voltage that is output from the amplifier to a ground potential.

6. The ADC of claim 1 , wherein the time-to-digital converter comprises:

a plurality of delay elements arranged in series;

a plurality of flip-flops, wherein the plurality of delay elements respectively have an output coupled to a first input of a corresponding one of the plurality of flip-flops and wherein the plurality of flip-flops further comprise a second input that is coupled to the output of the zero crossing detector; and

a thermometer code converter coupled to outputs of the plurality of flip-flops, wherein the thermometer code converter is configured to generate the second digital signal.

7. The ADC of claim 1 , wherein the amplifier comprises an open loop amplifier configured to provide the voltage-to-time conversion element with a low power consumption.

8. The ADC of claim 1 , further comprising:

a digital error correction circuit configured to receive the first digital signal and the second digital signal and to output a digital output signal.

9. The ADC of claim 1 , further comprising:

a residue offset circuit coupled to the input of the amplifier, wherein the residue offset circuit is configured to provide a residue offset voltage that causes the voltage-to-time conversion element to generate the time domain representation as a linear function.

10. An analog-to-digital converter (ADC), comprising:

a successive-approximation-register block configured to receive an input signal and to generate a first digital signal and a residue voltage;

a residue offset circuit configured to generate a residue offset voltage;

a conversion element comprising an amplifier that is configured to output an output voltage that is a function of the residue voltage and the residue offset voltage and a comparator configured to convert the output voltage to a time domain representation of the residue voltage; and

a time-to-digital converter configured to generate a second digital signal from the time domain representation.

11. The ADC of claim 10 , wherein the time domain representation that is output from the conversion element is a linear function.

12. The ADC of claim 10 , further comprising:

a discharge current source operably coupled to an input of the amplifier and an output of the successive-approximation-register block, wherein the discharge current source is configured to generate a discharge current; and

a capacitive element selectively coupled to a ground potential by way of a first switching element, to an offset voltage source by way of a second switching element, and to the discharge current source by way of a third switching element.

13. The ADC of claim 12 , further comprising:

a fourth switching element disposed between the discharge current source and the input of the amplifier.

14. The ADC of claim 12 , wherein the output voltage generated by the amplifier is proportional to a product of the discharge current and a gain of the amplifier.

15. A method of performing an analog to digital conversion, comprising:

operating a successive approximation register to generate a first digital signal and a residue voltage from an analog input signal;

operating a voltage-to-time conversion element to generate a time domain representation based upon the residue voltage and a residue offset voltage; and

operating a time-to-digital converter to generate a second digital signal based upon the time domain representation.

16. The method of claim 15 , further comprising:

generating a discharge current that is configured to cause the residue voltage to discharge from the successive approximation register.

17. The method of claim 15 , wherein the time domain representation is proportional to the residue offset voltage.

18. The method of claim 15 , wherein the time domain representation is a linear function.

19. The method of claim 15 , further comprising:

operating a first switching element to couple a discharge current from a discharge current source to an output of the successive approximation register at a first time; and

operating a second switching element to couple the output of the successive approximation register to an input of the voltage-to-time conversion element at a second time after the first time.

20. The method of claim 19 , further comprising:

operating the first switching element to decouple the discharge current from the output of the successive approximation register at a third time after the second time; and

operating the second switching element to decouple the output of the successive approximation register from the input of the voltage-to-time conversion element at the third time.