Digital oversampling clock and data recovery circuit
In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.
1. An apparatus comprising:
an analog front end to receive a digital input, the analog front end to output a data stream from the digital input;
a first counter to count a first count value corresponding to a first duration of a sample of the data stream responsive to detection of a first edge in the data stream, wherein the first counter is to be asynchronously reset responsive to the first edge detection;
a second counter to count a second count value corresponding to a second duration of another sample of the data stream responsive to detection of a second edge in the data stream, wherein the second counter is to be asynchronously reset responsive to the second edge detection;
a filter to filter a count value obtained based at least in part on the first count value and the second count value; and
a digitally controlled oscillator to generate a recovery clock signal from the filtered count value.
2. The apparatus of claim 1 , wherein the apparatus comprises a clock and data recovery circuit having an open loop configuration, the clock and data recovery circuit further comprising:
a first summer to receive the first count value and sum the first count value with a first predetermined value to generate the count value, the first predetermined value comprising a ratio between a system clock signal and the recovery clock signal; and
a second summer to receive the filtered count value and sum the filtered count value with the first predetermined value to generate a summed filtered count value, and provide the summed filtered count value to the digitally controlled oscillator.
3. The apparatus of claim 2 , wherein the filter comprises a configurable finite impulse response filter.
4. The apparatus of claim 3 , wherein the configurable finite impulse response filter has a dynamically configurable order based on a type of the digital input.
5. The apparatus of claim 2 , wherein the filter is to be clocked by a first clock signal based on the system clock signal.
6. The apparatus of claim 1 , wherein the apparatus comprises a clock and data recovery circuit having a closed loop configuration, the clock and data recovery circuit further comprising:
a first summer to receive the first count value and sum the first count value with a first feedback signal to generate the count value; and
a second summer to receive the filtered count value and sum the filtered count value with a first predetermined value to generate the first feedback signal, wherein the filtered count value comprises the first feedback signal to be provided to the digitally controlled oscillator, the first predetermined value comprising a ratio between a system clock signal and the recovery clock signal.
7. The apparatus of claim 6 , wherein the filter comprises a configurable finite impulse response filter.
8. The apparatus of claim 7 , wherein the configurable finite impulse response filter has a dynamically configurable order based on a type of the digital input.
9. The apparatus of claim 7 , wherein the filter further comprises a low pass filter coupled to an output of the configurable finite impulse response filter.
10. The apparatus of claim 9 , wherein the low pass filter is to be clocked with the recovery clock signal coupled in feedback from the digitally controlled oscillator.
11. The apparatus of claim 6 , wherein the filter is to be clocked by a first clock signal based on the system clock signal.
12. The apparatus of claim 1 , further comprising an edge detector to receive the data stream, the edge detector to detect the first edge and the second edge.
13. The apparatus of claim 1 , wherein the analog front end is further to receive a reference voltage and compare the digital input to the reference voltage.
14. The apparatus of claim 1 , further comprising a clock and data recovery core to receive the data stream and provide the recovery clock signal and recovered data to a consuming circuit.
15. A system comprising:
a universal serial bus (USB) interface circuit including a clock and data recovery (CDR) circuit, the CDR circuit comprising:
an analog front end to receive a digital input, the analog front end to output a data stream from the digital input;
a first counter to count a first count value corresponding to a first duration of a sample of the data stream responsive to detection of a first edge in the data stream, wherein the first counter is to be asynchronously reset responsive to the first edge detection;
a second counter to count a second count value corresponding to a second duration of another sample of the data stream responsive to detection of a second edge in the data stream, wherein the second counter is to be asynchronously reset responsive to the second edge detection;
a filter to filter a count value obtained based at least in part on the first count value and the second count value; and
a digitally controlled oscillator to generate a recovery clock signal from the filtered count value;
a battery coupled to the USB interface circuit, the battery to receive charging current via the USB interface circuit; and
a voltage regulator coupled to the battery, the battery to provide a voltage to the voltage regulator.
16. The system of claim 15 , further comprising:
a first summer to receive the first count value and sum the first count value with a first feedback signal to generate the count value; and
a second summer to receive the filtered count value and sum the filtered count value with a first predetermined value to generate the first feedback signal, wherein the filtered count value comprises the first feedback signal to be provided to the digitally controlled oscillator, the first predetermined value comprising a ratio between a system clock signal and the recovery clock signal.
17. A method comprising:
receiving, in an analog front end of a receiver, a digital input, and outputting a data stream from the digital input;
counting, in a first counter, a first count value corresponding to a first duration of a sample of the data stream responsive to detection of a first edge in the data stream, wherein the first counter is to be asynchronously reset responsive to the first edge detection;
counting, in a second counter, a second count value corresponding to a second duration of another sample of the data stream responsive to detection of a second edge in the data stream, wherein the second counter is to be asynchronously reset responsive to the second edge detection;
filtering, in a filter, a count value obtained based at least in part on the first count value and the second count value;
generating, in a digitally controlled oscillator, a recovery clock signal from the filtered count value; and
sending the recovery clock signal to a consuming circuit.
18. The method of claim 17 , further comprising:
summing, in a first summer, the first count value with a first feedback signal to generate the count value; and
summing, in a second summer the filtered count value with a first predetermined value to generate the first feedback signal; and
providing the filtered count value to the digitally controlled oscillator, wherein the filtered count value comprises the first feedback signal and the first predetermined value comprises a ratio between a system clock signal and the recovery clock signal.
19. The method of claim 17 , further comprising:
dynamically configuring an order of a configurable finite impulse response filter based on a type of the digital input; and
filtering the count value in the configurable finite impulse response filter.
20. The method of claim 19 , further comprising clocking a low pass filter coupled to an output of the configurable finite impulse response with the recovery clock signal coupled in feedback from the digitally controlled oscillator.