Integrated circuit including ferroelectric memory cells and methods for manufacturing
Integrated circuits including a ferroelectric memory cell and methods for manufacturing the same. One embodiment of the memory cells include three main layers: a first oxide ferroelectric layer, a second oxide anti-ferroelectric layer, and a covering layer. The ferroelectric material of the first and second oxides include as main components oxygen and any of the group containing Hf, Zr, and (Hf, Zr).
1. An integrated circuit comprising a ferroelectric memory cell, the ferroelectric memory cell comprising:
a first oxide layer;
a second oxide layer;
a third oxide layer; and
a covering layer on at least one oxide layer,
wherein the first and third oxide layers comprise a material that is at least partly in a ferroelectric state and comprises, as main components, oxygen and any of the group consisting of: Hf, Zr, and (Hf, Zr); and
wherein the second oxide layer is disposed between the first and third oxide layers; and
wherein the second oxide layer comprises a material that has an antiferroelectric crystalline structure.
2. An integrated circuit comprising a ferroelectric memory cell, the ferroelectric memory cell comprising:
a first oxide layer;
a second oxide layer;
a third oxide layer; and
a covering layer on at least one oxide layer,
wherein the first and third oxide layers comprise a material that is at least partly in a ferroelectric state and comprises, as main components, oxygen and any of the group consisting of: Hf, Zr, and (Hf, Zr);
wherein the second oxide layer is disposed between the first and third oxide layers; and
wherein the second oxide layer is an amorphous layer with antiferroelectric crystalline inclusions.
3. The integrated circuit of claim 1 wherein the first and third oxide layers comprise further additives of a concentration within a range of 0.5% to 6.75% and the additives are at least one of the C, Si, Al, Ge, Sn, Sr, Pb, Mg, Ca, Sr, Ba, Ti, Zr, and one or more rare earth elements.
4. The integrated circuit of claim 1 wherein:
the second oxide layer overlies the first; and
the third oxide layer overlies the first and second; and
the covering layer comprises at least one of TiN, TaN, TaCN, WCN, Ru, Re, RuO, Pt, Ir, IrO Ti, TiAlN, TaAlN, W, WN, C, Si, Ge, SiGe, and NbCN.
5. The integrated circuit of claim 1 wherein the second oxide layer contains nanodots comprising a ferroelectric material that is at least partly in a ferroelectric state and comprising, as main components, oxygen and any of the group consisting of: Hf, Zr, and (Hf, Zr).
6. The integrated circuit of claim 1 wherein the second oxide layer comprises further additives of a concentration within a range of 0.5% to 20% and the additives are at least one of the C, Si, Al, Ge, Sn, Sr, Pb, Mg, Ca, Sr, Ba, Ti, Zr, and one or more rare earth elements.
7. The integrated circuit of claim 1 wherein the thicknesses of the first and third oxide layers are in the range of 1 Angstrom to 150 Angstroms.
8. The integrated circuit of claim 1 wherein the first and third oxide layers are about the same thickness.
9. The integrated circuit of claim 1 wherein the first and third oxide layers have different thicknesses.
10. The integrated circuit of claim 1 wherein the first and third oxide layers have separate polarization states.
11. The integrated circuit of claim 1 wherein the second and third oxide layers form a stacking layer; and
wherein a plurality of stacking layers forms a system that overlies the first oxide layer; and
wherein the orientation of the stacking layers is such that a second oxide layer is always adjacent to a first or third oxide layer.
12. The integrated circuit of claim 11 wherein the first oxide layer and each stacking layer have separate polarization states.
13. The integrated circuit of claim 2 wherein the first and third oxide layers comprise further additives of a concentration within a range of 0.5% to 6.75% and the additives are at least one of the C, Si, Al, Ge, Sn, Sr, Pb, Mg, Ca, Sr, Ba, Ti, Zr, and one or more rare earth elements.
14. The integrated circuit of claim 2 wherein the first oxide layer overlies the second and third oxide layers, and the covering layer comprises at least one of TiN, TaN, TaCN, WCN, Ru, Re, RuO, Pt, Ir, IrO, Ti, TiAlN, TaAlN, W, WN, C, Si, Ge, SiGe, and NbCN.
15. The integrated circuit of claim 2 wherein the thicknesses of the first and third oxide layers are in the range of 1 Angstrom to 150 Angstroms.
16. The integrated circuit of claim 2 wherein the first and third oxide layers are about the same thickness.
17. The integrated circuit of claim 2 wherein the first and third oxide layers have different thicknesses.
18. The integrated circuit of claim 2 wherein the first and third oxide layer have separate polarization states.