Non-switched capacitor circuits for delta-sigma ADCs
Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.
1. A differential integrator circuit operating in sampling and integration phases, comprising:
a positive input voltage;
a negative input voltage;
an op amp having an inverting input, a non-inverting input, an inverting output, and a non-inverting output;
a first sampling capacitor;
a first integration capacitor; and
a first non-switched capacitor,
wherein:
the first integration capacitor is coupled between the inverting input and the non-inverting output of the op amp,
the first non-switched capacitor is coupled between the negative input voltage and the inverting input of the op amp,
during the sampling phase, the positive input voltage is coupled to the first sampling capacitor, and
during the integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.
2. The differential integrator circuit in claim 1 further comprising:
a second sampling capacitor;
a second integration capacitor; and
a second non-switched capacitor,
wherein:
the second integration capacitor is coupled between the non-inverting input and the inverting output of the op amp,
the second non-switched capacitor is coupled between the positive input voltage and the non-inverting input of the op amp,
during the sampling phase, the negative input voltage is coupled to the second sampling capacitor, and
during the integration phase, a charge sampled across the second sampling capacitor is transferred to the second integration capacitor.
3. The differential integrator circuit in claim 2 further comprising:
a discrete-time integrator circuit having first and second outputs,
wherein the first output is in electrical communication with the positive input voltage and the second output is in electrical communication with the negative input voltage.
4. The differential integrator circuit in claim 3 wherein the discrete-time integrator circuit is a delayless integrator.
5. The differential integrator circuit in claim 3 further comprising:
an analog-to-digital converter (ADC); and
a digital-to-analog converter (DAC),
wherein:
the ADC is coupled to the inverting output and the non-inverting output of the op amp, and
an output of the ADC is coupled to an input of the DAC.
6. The differential integrator circuit in claim 5 wherein the ADC is a flash ADC.
7. The differential integrator circuit in claim 5 wherein the DAC is a switched-capacitor type.
8. The differential integrator circuit in claim 5 wherein the DAC is coupled to an input of the discrete-time integrator circuit.
9. A delta-sigma analog-to-digital converter comprising:
a first integrator circuit operating in sampling and integration phases, the first integrator circuit comprising:
a positive integrator input voltage;
a negative integrator input voltage;
an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output;
a first sampling capacitor;
a first integration capacitor; and
a first non-switched capacitor;
an analog-to-digital converter having an ADC input coupled to the inverting output and the non-inverting output of the op amp; and
a digital-to-analog converter having a DAC input coupled to an ADC output of the analog-to-digital converter,
wherein:
the first integration capacitor is coupled between the inverting input and the non-inverting output of the op amp,
the first non-switched capacitor is coupled between the negative integrator input voltage and the inverting input of the op amp,
during the sampling phase, the positive integrator input voltage is coupled to the first sampling capacitor, and
during the integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.
10. The delta-sigma analog-to-digital converter of claim 9 further comprising:
a second integrator circuit having a first output and a second output,
wherein the first output is in electrical communication with the positive integrator input voltage and the second output is in electrical communication with the negative integrator input voltage.
11. The delta-sigma analog-to-digital converter of claim 10 wherein the second integrator is a discrete-time integrator.
12. The delta-sigma analog-to-digital converter of claim 10 wherein the second integrator is a continuous-time integrator.
13. The delta-sigma analog-to-digital converter of claim 9 further comprising:
a discrete-time integrator circuit having a first output and a second output; and
a continuous-time integrator,
wherein:
the first output of the discrete-time integrator circuit is in electrical communication with the positive integrator input voltage and the second output of the discrete-time integrator circuit is in electrical communication with the negative integrator input voltage,
a positive output of the continuous-time integrator is in electrical communication with a positive input of the discrete-time integrator circuit, and
a negative output of the continuous-time integrator is in electrical communication with a negative input of the discrete-time integrator circuit.