IP Library › Granted Patent US 10,469,783
Granted Patent B2
US 10,469,783 · App. 16/067,316 · Granted Nov 5, 2019

Solid-state image sensor and imaging apparatus

Inventors: Yoshimichi Kumagai (Kanagawa, JP); Takashi Abe (Kanagawa, JP); Kazuyoshi Yamashita (Kanagawa, JP); Ryoto Yoshita (Kanagawa, JP)
Assignee: SONY CORPORATION
H04N5/37452H01L27/146H01L27/1461H01L27/14603H01L27/14612H04N5/357H04N5/361H04N5/37457
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Quick Facts
Patent No.
US 10,469,783
App. No.
16/067,316
Granted
Nov 5, 2019
Kind
B2
Abstract

To transfer all charges retained in a charge retention region. The photoelectric converter generates a charge corresponding to the exposure amount during a predetermined exposure period. The generated-charge retention portion and the output charge retention portion retain the charge. The generated-charge transfer portion transfers the charge from the photoelectric converter to the generated-charge retention portion to perform the generated-charge transfer after the elapse of the exposure period. The retained-charge transfer portion transfers the charge retained in the generated-charge retention portion to the output charge retention portion to perform the retained-charge transfer. The generated-charge retention gate portion applies a control voltage that is a voltage for controlling potential of the generated-charge retention portion to the generated-charge retention portion during a period of the generated-charge transfer and the retained-charge transfer, applies a bias voltage that is a voltage having a polarity different from the control voltage to the generated-charge retention portion during a period different from the period of the generated-charge transfer and the retained-charge transfer, and applies the bias voltage to the generated-charge retention portion after applying an approximately intermediate voltage between the control voltage and the bias voltage to the generated-charge retention portion at the end of the period of the retained-charge transfer.

Claims (35)

1. A solid-state image sensor comprising:

a photoelectric converter configured to generate a charge corresponding to an exposure amount during a predetermined exposure period;

a generated-charge retention portion formed in a semiconductor region and configured to retain the charge;

a generated-charge transfer portion configured to transfer the charge from the photoelectric converter to the generated-charge retention portion to perform generated-charge transfer by allowing electrical conduction between the photoelectric converter and the generated-charge retention portion after an elapse of the exposure period;

an output charge retention portion configured to retain the charge;

a retained-charge transfer portion configured to transfer the charge retained in the generated-charge retention portion to the output charge retention portion to perform retained-charge transfer by allowing electrical conduction between the generated-charge retention portion and the output charge retention portion;

a signal generation portion configured to generate a signal corresponding to the charge retained in the output charge retention portion as an image signal after the retained-charge transfer; and

a generated-charge retention gate portion configured to apply a control voltage for controlling potential of the generated-charge retention portion to the generated-charge retention portion during a period of the generated-charge transfer and the retained-charge transfer, apply a bias voltage having a polarity different from the control voltage to the generated-charge retention portion during a period different from the period of the generated-charge transfer and the retained-charge transfer, and apply the bias voltage to the generated-charge retention portion after applying an approximately intermediate voltage between the control voltage and the bias voltage to the generated-charge retention portion at an end of the period of the retained-charge transfer.

2. The solid-state image sensor according to claim 1 ,

wherein the generated-charge retention gate portion applies a voltage of approximately 0 V to the generated-charge retention portion as the approximately intermediate voltage between the control voltage and the bias voltage.

3. The solid-state image sensor according to claim 1 ,

wherein the generated-charge retention gate portion includes a plurality of electrodes and, when a change in voltages to be applied at an end of the retained-charge transfer from the control voltage to the bias voltage is performed, performs the change sequentially starting from an electrode arranged at a position far from the retained-charge transfer portion among the plurality of electrodes.

4. The solid-state image sensor according to claim 1 , further comprising:

a semiconductor region arranged between the generated-charge retention portion and the generated-charge retention gate and formed to have a conductivity type different from a conductivity type of the semiconductor region in which the generated-charge retention portion is formed.

5. The solid-state image sensor according to claim 1 , further comprising:

a charge discharger configured to discharge the charge retained in the output charge retention portion before the retained-charge transfer.

6. The solid-state image sensor according to claim 5 ,

wherein the charge discharger is made nonconductive during the period of the retained-charge transfer for discharging the charge remaining in the generated-charge retention portion before the generated-charge transfer.

7. The solid-state image sensor according to claim 1 ,

wherein the generated-charge retention gate portion is applied with the control voltage before making the retained-charge transfer portion conductive in the retained-charge transfer.

8. The solid-state image sensor according to claim 1 ,

wherein the retained-charge transfer portion further includes a retained-charge transfer gate in which application of an on-voltage used to make the retained-charge transfer portion conductive and application of an off-voltage having a polarity different from a polarity of the on-voltage are performed.

9. The solid-state image sensor according to claim 8 ,

wherein, in the retained-charge transfer portion, the off-voltage is applied to the retained-charge transfer gate after an approximately intermediate voltage between the on-voltage and the off-voltage is applied to the retained-charge transfer gate at the end of the period of the retained-charge transfer.

10. The solid-state image sensor according to claim 9 ,

wherein, in the retained-charge transfer portion, a voltage of approximately 0 V is applied to the retained-charge transfer gate as the approximately intermediate voltage between the on-voltage and the off-voltage.

11. An imaging apparatus comprising:

a photoelectric converter configured to generate a charge corresponding to an exposure amount during a predetermined exposure period;

a generated-charge retention portion formed in a semiconductor region and configured to retain the charge;

a generated-charge transfer portion configured to transfer the charge from the photoelectric converter to the generated-charge retention portion to perform generated-charge transfer by allowing electrical conduction between the photoelectric converter and the generated-charge retention portion after an elapse of the exposure period;

an output charge retention portion configured to retain the charge;

a retained-charge transfer portion configured to transfer the charge retained in the generated-charge retention portion to the output charge retention portion to perform retained-charge transfer by allowing electrical conduction between the generated-charge retention portion and the output charge retention portion;

a signal generation portion configured to generate a signal corresponding to the charge retained in the output charge retention portion as an image signal after the retained-charge transfer;

a generated-charge retention gate portion configured to apply a control voltage for controlling potential of the generated-charge retention portion to the generated-charge retention portion during a period of the generated-charge transfer and the retained-charge transfer, apply a bias voltage having a polarity different from the control voltage to the generated-charge retention portion during a period different from the period of the generated-charge transfer and the retained-charge transfer, and apply the bias voltage to the generated-charge retention portion after applying an approximately intermediate voltage between the control voltage and the bias voltage to the generated-charge retention portion at an end of the period of the retained-charge transfer; and

a processing circuit configured to process the generated signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2018
From: KUMAGAI, YOSHIMICHI; ABE, TAKASHI; YAMASHITA, KAZUYOSHI; YOSHITA, RYOTO
To: SONY CORPORATION
Reel/Frame 046238/0797 →
Priority Claims (1)
JP 2016-009365 · Jan 21, 2016 · national
Continuity (1)
Related Publication 20190014278A1 · Jan 10, 2019