Enabling system low power state when compute elements are active
Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.
1. An apparatus comprising:
logic, at least a portion of which is in hardware, to cause a fabric and a memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while a compute element, coupled to the fabric and the memory controller, is in an active state,
wherein the memory controller and the fabric are to be shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is to be prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.
2. The apparatus of claim 1 , wherein the active state is to comprise an operating state in which the compute element is executing one or more operations by accessing a local memory or cache of the compute element instead of accessing a main memory.
3. The apparatus of claim 2 , wherein a System On Chip (SOC) integrated circuit is to comprise the logic, the fabric, and the memory controller, wherein the main memory is external to the SOC.
4. The apparatus of claim 2 , wherein the logic is to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to the main memory entering a self-refresh operation.
5. The apparatus of claim 1 , wherein a system on chip integrated circuit is to comprise the logic, the fabric, and the memory controller.
6. The apparatus of claim 1 , wherein the compute element is to comprise one or more of: a processor, having one or more processor cores, a graphics processing unit, image processing logic, or media processing logic.
7. The apparatus of claim 1 , wherein a memory subsystem on an SOC integrated circuit is to comprise the memory controller and a physical input/output interface.
8. The apparatus of claim 1 , wherein the logic is to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more hardware events in an SOC integrated circuit.
9. The apparatus of claim 1 , wherein the logic is to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more software hints in an SOC integrated circuit.
10. A method comprising:
causing a fabric and a memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while a compute element, coupled to the fabric and the memory controller, is in an active state,
wherein the memory controller and the fabric are shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.
11. The method of claim 10 , wherein the active state comprises an operating state in which the compute element is executing one or more operations by accessing a local memory or cache of the compute element instead of accessing a main memory.
12. The method of claim 11 , further comprising causing the fabric and the memory controller to enter the low power consumption state at least partially in response to the main memory entering a self-refresh operation.
13. The method of claim 11 , further comprising coupling the memory controller to the main memory via a physical input/output interface.
14. The method of claim 10 , further comprising causing the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more hardware events in an SOC integrated circuit.
15. The method of claim 10 , further comprising causing the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more software hints in an SOC integrated circuit.
16. A non-transitory computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
cause a fabric and a memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while a compute element, coupled to the fabric and the memory controller, is in an active state,
wherein the memory controller and the fabric are to be shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is to be prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.
17. The non-transitory computer-readable medium of claim 16 , wherein the active state comprises an operating state in which the compute element is executing one or more operations by accessing a local memory or cache of the compute element instead of accessing a main memory.
18. The non-transitory computer-readable medium of claim 16 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to the main memory entering a self-refresh operation.
19. The non-transitory computer-readable medium of claim 16 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more hardware events in an SOC integrated circuit.
20. The non-transitory computer-readable medium of claim 16 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to occurrence of one or more software hints in an SOC integrated circuit.
21. A computing system comprising:
memory to store data to be accessed by one or more processor cores of on an SOC integrated circuit device, wherein the memory is external to the SOC integrated circuit device;
the SOC integrated circuit device to comprise a fabric, a memory controller, coupled to the memory, and logic, at least a portion of which is in hardware, to cause the fabric and the memory controller to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle and while one or more of the one or more processor cores are in an active state,
wherein the memory controller and the fabric are to be shared amongst a plurality of components of a System on Chip (SOC) device, wherein the plurality of components of the SOC comprise the fabric, the memory controller, and the compute element, wherein the compute element is to be prevented from accessing the shared fabric and the shared memory controller in response to a determination that the fabric and the memory controller have entered the low power consumption state.
22. The system of claim 21 , wherein the active state is to comprise an operating state in which at least one of the one or more processor cores is executing one or more operations by accessing a local memory or cache of the compute element instead of accessing the memory.
23. The system of claim 21 , wherein the logic is to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to the memory entering a self-refresh operation.
24. The system of claim 21 , wherein a memory subsystem on the SOC integrated circuit is to comprise the memory controller and a physical input/output interface.
25. The system of claim 21 , wherein the logic is to cause the fabric and the memory controller to enter the low power consumption state at least partially in response to one or more: occurrence of one or more hardware events in an SOC integrated circuit or occurrence of one or more software hints in an SOC integrated circuit.