Host-assisted error recovery

1. An apparatus comprising:

a data storage drive including:

an interface to communicate with a host device;

a nonvolatile solid state memory;

a processor configured to:

calculate parity data based on a plurality of pages from the nonvolatile solid state memory; and

provide, in response to a request for the parity data received from the host device via the interface, the parity data to the host device with an indication to store the parity data to a nonvolatile storage medium.

2. The apparatus of claim 1 further comprising:

the indication to store the parity data includes an identifier used to request the parity data from the host device for error correction.

3. The apparatus of claim 2 further comprising:

the processor further configured to:

receive a read request from the host device for stored data stored to a page from the plurality of pages;

perform a read operation for the stored data;

when a read error is encountered during the read operation:

return an error indicator to the host device;

provide the identifier to the host device for the parity data;

receive an error correction request from the host including the parity data; and

perform error correction based on the parity data to recover the stored data.

4. The apparatus of claim 1 further comprising:

the processor further configured to:

receive a write request from the host device including host data to store to the nonvolatile solid state memory;

store the host data to a selected page having a first offset within a first block of the nonvolatile solid state memory;

generate the parity data based on the selected page from the first block and other pages at the first offset within other blocks of the nonvolatile solid state memory;

receive a parity data request from the host device; and

provide the parity data to the host device in response to the parity data request.

5. The apparatus of claim 1 further comprising:

the processor further configured to:

perform garbage collection on blocks of the nonvolatile solid state memory;

generate new sets of parity data based on pages from the blocks that were garbage collected; and

provide the new sets of parity data to the host device in response to a request from the host for the parity data.

6. The apparatus of claim 1 further comprising:

the nonvolatile solid state memory includes Flash memory; and

the processor further configured to generate the parity data based on a corresponding page from a corresponding block from each memory die of the Flash memory.

7. A system comprising:

a data storage drive including:

an interface to communicate with a host device;

a nonvolatile solid state memory;

a controller configured to:

calculate parity data based on a plurality of pages from the nonvolatile solid state memory;

receive a request for the parity data from the host device;

provide, via the interface in response to the request, the parity data to the host device with an indication to store the parity data to a nonvolatile storage medium;

the host device, including a processor configured to:

send the request to the data storage drive; and

store the parity data to a persistent memory internal to the host device.

8. The system of claim 7 further comprising:

the indication to store the parity data includes an identifier used to request the parity data from the host for error correction; and

the processor configured to store the parity data to a location of the persistent memory selected based on the identifier.

9. The system of claim 8 further comprising:

the controller further configured to:

receive a read request from the host device for stored data stored to a page from the plurality of pages;

perform a read operation for the stored data;

when a read error is encountered during the read operation:

return an error indicator to the host device;

provide the identifier to the host device for the parity data;

receive an error correction request from the host including the parity data;

perform error correction based on the parity data to recover the stored data;

the processor configured to:

issue the read request;

retrieve the parity data from the persistent memory based on the identifier using drivers installed at the host to facilitate storage and retrieval of the parity data; and

issue the error correction request.

10. The system of claim 7 further comprising:

the controller further configured to:

receive a write request from the host device including host data to store to the nonvolatile solid state memory;

store the host data to a selected page of the nonvolatile solid state memory;

generate the parity data based on the selected page from a first block and corresponding pages from other blocks of the nonvolatile solid state memory;

receive a parity data request from the host device; and

provide the parity data to the host device in response to the parity data request; and

the processor configured to issue the parity data request at selected time intervals.

11. The system of claim 7 further comprising:

the controller further configured to:

perform garbage collection on blocks of the nonvolatile solid state memory;

generate new sets of parity data based on pages from the blocks that were garbage collected; and

provide the new sets of parity data to the host device in response to a request from the host for the parity data.

12. The system of claim 7 further comprising:

the nonvolatile solid state memory includes Flash memory;

the controller further configured to generate the parity data based on a corresponding page from a corresponding block from each memory die of the Flash memory; and

the persistent memory includes a hard disc drive.

13. A method comprising:

calculating parity data based on a plurality of pages from a nonvolatile solid state memory at a data storage drive; and

receive a parity data request from a host device;

responding to the parity data request by providing the parity data from the data storage drive to the host device with an indication to store the parity data to a nonvolatile storage medium of the host device.

14. The method of claim 13 further comprising:

providing, along with the parity data and the indication, an identifier for the parity data used to request the parity data from the host device for error correction.

15. The method of claim 14 further comprising:

receiving a read request from the host device for stored data stored to a page from the plurality of pages;

performing a read operation for the stored data;

when a read error is encountered during the read operation:

returning an error indicator to the host device;

providing the identifier to the host device for the parity data;

receiving an error correction request from the host device including the parity data; and

performing error correction based on the parity data to recover the stored data.

16. The method of claim 13 further comprising:

receiving a write request from the host device including host data to store to the nonvolatile solid state memory;

storing the host data to a selected page having a first offset within a first block of the nonvolatile solid state memory; and

generating the parity data based on the selected page from the first block and other pages at the first offset of other blocks of the nonvolatile solid state memory in response to the parity data request.

17. The method of claim 13 further comprising:

performing garbage collection on blocks of the nonvolatile solid state memory;

generating new sets of parity data based on pages from the blocks that were garbage collected; and

providing the new sets of parity data to the host device in response to a request from the host for the parity data.

18. The method of claim 16 wherein:

the parity data comprises an outer code (OC) parity page; and

the plurality of pages comprise a parity stripe, the parity stripe including a set of pages at a selected page offset of a plurality of blocks of the solid state memory.

19. The system of claim 10 wherein:

the parity data comprises an outer code (OC) parity page; and

the plurality of pages comprise a parity stripe, the parity stripe including a set of pages at a selected page offset of a plurality of blocks of the solid state memory.

20. The apparatus of claim 1 further comprising:

the processor further configured to calculate the parity data as an outer code (OC) parity page based on the plurality of pages from the nonvolatile solid state memory that comprise a parity stripe.