IP Library › Granted Patent US 12,224,771
Granted Patent B2
US 12,224,771 · App. 18/513,278 · Granted Feb 11, 2025

Data reliability for extreme temperature usage conditions in data storage

Inventors: Poorna Kale (Folsom, CA); Christopher Joseph Bueb (Folsom, CA)
Assignee: Lodestar Licensing Group LLC
H03M13/2906G06F11/1068H03M13/353G11C16/0483
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,224,771
App. No.
18/513,278
Granted
Feb 11, 2025
Kind
B2
Abstract

After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Claims (37)

1. A device, comprising:

an array of non-volatile memory cells; and

a logic circuit configured to:

determine a condition of storing a set of data in the non-volatile memory cells for retrieval;

select, based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;

generate, based on the level selected for the condition, redundant data; and

store, in the non-volatile memory cells, the set of data and the redundant data.

2. The device of claim 1 , wherein the redundant data includes parity data.

3. The device of claim 1 , wherein the condition includes a temperature.

4. The device of claim 1 , wherein the condition includes a level of processing power to decode using the error correction techniques.

5. The device of claim 1 , wherein the condition includes a condition of power supply.

6. The device of claim 1 , wherein the logic circuit is operable to generate redundant data at a first predetermined level and a second predetermined level higher than the first predetermined level.

7. The device of claim 6 , wherein the logic circuit is operable to generate first parity data from first data to protect the first data at the first predetermined level, and generate the first parity data and second parity data from the first data to protect the first data at the second predetermined level.

8. The device of claim 1 , wherein the condition is determined based on a machine learning model and sensor data.

9. The device of claim 8 , further comprising:

a sensor configured to generate inputs to the machine learning mode to generate a prediction indicative of the condition.

10. A method, comprising:

determining, by a computing device, a condition of storing a set of data in an array of non-volatile memory cells of the computing device for retrieval;

selecting, by the computing device based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;

generating, by the computing device based on the level selected for the condition, redundant data; and

storing, in the non-volatile memory cells, the set of data and the redundant data.

11. The method of claim 10 , wherein the redundant data includes parity data.

12. The method of claim 10 , wherein the condition includes a temperature.

13. The method of claim 10 , wherein the condition includes a level of processing power to decode using the error correction techniques.

14. The method of claim 10 , wherein the condition includes a condition of power supply.

15. The method of claim 10 , wherein the computing device is operable to generate redundant data at a first predetermined level and a second predetermined level higher than the first predetermined level.

16. The method of claim 15 , wherein generation of redundant data at the first predetermined level includes generating first parity data from first data to protect the first data at the first predetermined level, and generation of redundant data at the second predetermined level includes generating the first parity data and second parity data from the first data to protect the first data at the second predetermined level.

17. The method of claim 10 , wherein the condition is determined based on a machine learning model and sensor data.

18. The method of claim 17 , further comprising:

generating, by a sensor configured in the computing device, inputs to the machine learning mode to generate a prediction indicative of the condition.

19. A non-transitory computer storage medium storing instructions which when executed by a computing device, cause the computing device to perform a method, comprising:

determining, by the computing device, a condition of storing a set of data in an array of non-volatile memory cells of the computing device for retrieval;

selecting, by the computing device based on the condition, a level of redundancy configured to protect the set of data via error correction techniques;

generating, by the computing device based on the level selected for the condition, redundant data; and

storing, in the non-volatile memory cells, the set of data and the redundant data.

20. The non-transitory computer storage medium of claim 19 , wherein the generating of the redundant data at a first predetermined level includes generating first parity data from first data to protect the first data at the first predetermined level; and

wherein the generating of the redundant data at a second predetermined level includes generating the first parity data and second parity data from the first data to protect the first data at the second predetermined level.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 069595/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2024
From: KALE, POORNA; BUEB, CHRISTOPHER JOSEPH
To: MICRON TECHNOLOGY, INC.
Reel/Frame 069596/0212 →
Continuity (3)
Continuation 17694280 · Mar 14, 2022
Continuation 16937077 · Jul 23, 2020
Related Publication 20240088918A1 · Mar 14, 2024
References Cited (32)
US 7000168B2 · Kurtas et al. · 2006 [cited by applicant]
US 8291285B1 · Varnica et al. · 2012 [cited by applicant]
US 8621318B1 · Micheloni et al. · 2013 [cited by applicant]
US 8645789B2 · Sharon et al. · 2014 [cited by applicant]
US 8650463B2 · Lim et al. · 2014 [cited by applicant]
US 8924815B2 · Frayer et al. · 2014 [cited by applicant]
US 10417089B2 · Oboukhov et al. · 2019 [cited by applicant]
US 10474527B1 · Sun · 2019 [cited by applicant]
US 11164652B2 · Subbarao et al. · 2021 [cited by applicant]
US 11296729B2 · Kale · 2022 [cited by examiner]
US 11676679B2 · Subbarao et al. · 2023 [cited by applicant]
US 11870463B2 · Kale · 2024 [cited by examiner]
US 20060075321A1 · Vedantham et al. · 2006 [cited by applicant]
US 20080163023A1 · Hong · 2008 [cited by examiner]
US 20130301371A1 · Chen · 2013 [cited by examiner]
US 20130305120A1 · Torii et al. · 2013 [cited by applicant]
US 20140153654A1 · Vojcic et al. · 2014 [cited by applicant]
US 20140208186A1 · Stek et al. · 2014 [cited by applicant]
US 20150043281A1 · Hemink · 2015 [cited by examiner]
US 20170046221A1 · Bandic et al. · 2017 [cited by applicant]
US 20180032395A1 · Yang et al. · 2018 [cited by applicant]
US 20180219561A1 · Litsyn et al. · 2018 [cited by applicant]
US 20180287639A1 · Murakami · 2018 [cited by applicant]
US 20190140784A1 · Xi et al. · 2019 [cited by applicant]
US 20200402605A1 · Subbarao et al. · 2020 [cited by applicant]
US 20210407612A1 · Subbarao et al. · 2021 [cited by applicant]
US 20220029641A1 · Kale et al. · 2022 [cited by applicant]
US 20220200630A1 · Kale et al. · 2022 [cited by applicant]
KR 101684157 · 2016 [cited by applicant]
International Search Report and Written Opinion, PCT/US2020/037297, mailed on Sep. 21, 2020. [cited by applicant]
Liva, et al. “Pivoting algorithms for maximum likelihood decoding of LDPC codes over erasure channels.” IEEE, 2009. [cited by applicant]
Savin, et al. “Binary linear time erasure decoding for non-binary LDPC codes.” IEEE, 2009. [cited by applicant]