Word-line driver and method of operating a word-line driver

1. A word-line driver coupled to an array of memory cells, the word-line driver comprising:

a decoder powered by a first power supply and being configured to decode an address to provide a plurality of word-line signals;

a plurality of output stages powered by a second power supply that is different than the first power supply, each of the output stages including

a first transistor having a gate controlled by a first control signal, and

an inverter coupled between the first transistor and a ground, the inverter having an input coupled to the decoder to receive one of the word-line signals; and

pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal, the pull-down circuitry configured to pull down gate voltages of transistors of the output stages to a low voltage.

2. The word-line driver of claim 1 , wherein

the pull-down circuitry comprises one or more second transistors coupled between the gates of the first transistors and the ground, each of the second transistors including a gate controlled by the second control signal.

3. The word-line driver of claim 2 , wherein a number of the second transistors is less than a number of the first transistors.

4. The word-line driver of claim 1 , wherein

the first transistor comprises a PMOS transistor coupled to the second power supply; and

the inverter comprises (i) a second PMOS transistor coupled to the first PMOS transistor and having a gate controlled by the one of the word-line signals, and (ii) a first NMOS transistor coupled between the second PMOS transistor and the ground.

5. The word-line driver of claim 4 , wherein the pull-down circuitry comprises one or more second NMOS transistors coupled between the gates of the first transistors and the ground, the one or more second NMOS transistors having gates controlled by the second control signal.

6. The word-line driver of claim 1 , wherein the inverter has an output electrically connected to a word line that is coupled to the array of memory cells.

7. The word-line driver of claim 1 , wherein

the first transistor is configured to provide power to the inverter based on a voltage of the first control signal.

8. The word-line driver of claim 1 , wherein the decoder comprises a plurality of decoder logic modules, each of the decoder logic modules being coupled to one or more output stages of the plurality of output stages.

9. A memory comprising:

an array of memory cells; and

a word-line driver configured to drive word lines coupled to the array of memory cells and including:

a decoder configured to decode an address to provide a plurality of word-line signals,

a plurality of output stages, each of the output stages (i) having an input coupled to the decoder to receive one of the word-line signals and (ii) configured to turn off based on a first control signal, and

control circuitry configured (i) to turn off the plurality of output stages in a standby mode during which the array of memory cells is not being accessed using the first control signal and (ii) pull gate voltages of transistors of the plurality of output stages to a low voltage, wherein the control circuitry is activated based on a second control signal.

10. The memory of claim 9 , further comprising:

a first power supply configured to power the decoder; and

a second power supply, different than the first power supply, configured to power the plurality of output stages.

11. The memory of claim 9 , wherein each of the output stages includes (i) a first transistor having a gate controlled by the first control signal, and (ii) an inverter coupled between the first transistor and a ground,

wherein the control circuitry is coupled between the gates of the first transistors and the ground.

12. The memory of claim 11 , wherein

the control circuitry comprises one or more second transistors coupled between the gates of the first transistors and the ground, each of the second transistors including a gate controlled by the second control signal.

13. The memory of claim 12 , wherein a number of the second transistors is less than a number of the first transistors.

14. The memory of claim 11 , wherein

the first transistor comprises a PMOS transistor coupled to the second power supply; and

the inverter comprises (i) a second PMOS transistor coupled to the first PMOS transistor and having a gate controlled by the one of the word-line signals, and (ii) a first NMOS transistor coupled between the second PMOS transistor and the ground.

15. The memory of claim 14 , wherein the control circuitry comprises one or more second NMOS transistors coupled between the gates of the first transistor and the ground, the one or more second NMOS transistors having gates controlled by the second control signal.

16. The memory of claim 9 , wherein the decoder comprises a plurality of decoder logic modules, each of the decoder logic modules being coupled to one or more output stages of the plurality of output stages.

17. A method for operating a word-line driver, the method comprising:

providing power to a decoder of the word-line driver using a first power supply;

decoding an address using the decoder to generate word-line signals;

transmitting the word-line signals to a plurality of output stages of the word-line driver, the plurality of output stages controlling voltage levels of word lines based on the word-line signals and being powered by a second power supply that is different than the first power supply, wherein the plurality of output stages are turned off based on a first control signal;

turning off the plurality of output stages when transitioning from an active mode of operation to a standby mode of operation; and

activating pull-down circuitry of the word-line driver based on a second control signal, the pull-down circuitry pulling gate voltages of transistors of the output stages to a low voltage.

18. The method of claim 17 , wherein the decoder is not turned off in the standby mode.

19. The method of claim 17 , further comprising:

turning on the plurality of output stages when transitioning from the standby mode of operation to the active mode of operation.

20. The method of claim 17 , further comprising:

providing power to the plurality of output stages based on a voltage of the first control signal.