IP Library › Granted Patent US 10,475,582
Granted Patent B2
US 10,475,582 · App. 15/869,473 · Granted Nov 12, 2019

Multilayer ceramic capacitor and method of manufacturing the same

Inventors: Hyuk Jin Hong (Suwon-si, KR); Doo Young Kim (Suwon-si, KR); Byung Soo Kim (Suwon-si, KR); Tae Young Sung (Suwon-si, KR); Youn Sik Jin (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/30H01G4/012H01G4/12H01G4/228H01G4/232H01G13/00
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Quick Facts
Patent No.
US 10,475,582
App. No.
15/869,473
Granted
Nov 12, 2019
Kind
B2
Abstract

A multilayer ceramic capacitor includes: a body including dielectric layers and first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively, wherein the body includes first dummy patterns formed adjacent to the first internal electrodes in a width direction to be spaced apart from the first internal electrodes, and the first dummy patterns are stacked to partially overlap the second internal electrodes.

Claims (35)

1. A multilayer ceramic capacitor comprising:

a body including dielectric layers and first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; and

first and second external electrodes disposed on the body opposing each other in a length direction, and connected to the first and second internal electrodes, respectively,

wherein the body includes first dummy patterns formed adjacent to the first internal electrodes in a width direction to be spaced apart from the first internal electrodes and extending along a length of the first internal electrodes, the first dummy patterns are insulated from, and not connected to, the first and second external electrodes, and

the first dummy patterns are stacked to partially overlap the second internal electrodes.

2. The multilayer ceramic capacitor of claim 1 , wherein end portions of the first internal electrodes in the width direction and end portions of the second internal electrodes in the width direction are disposed to be misaligned with each other.

3. The multilayer ceramic capacitor of claim 1 , wherein the first dummy patterns are formed of the same material as that of the first and second internal electrodes.

4. The multilayer ceramic capacitor of claim 1 , wherein the first dummy patterns are formed on opposite sides of the first internal electrodes in the width direction.

5. The multilayer ceramic capacitor of claim 1 , wherein widths of the first and second internal electrodes are different from each other.

6. The multilayer ceramic capacitor of claim 1 , wherein the body further includes second dummy patterns formed adjacent to the second internal electrodes in the width direction to be spaced apart from the second internal electrodes.

7. The multilayer ceramic capacitor of claim 6 , wherein the second dummy patterns are stacked to partially overlap the first internal electrodes.

8. The multilayer ceramic capacitor of claim 6 , wherein the first and second dummy patterns are not connected to the first and second external electrodes.

9. A multilayer ceramic capacitor comprising:

a body including dielectric layers and first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; and

first and second external electrodes disposed on the body and connected to the first and second internal electrodes, respectively,

wherein the body includes first dummy patterns formed adjacent to the first internal electrodes in a width direction to be spaced apart from the first internal electrodes, the first dummy patterns are not connected to, the first and second external electrodes, and second dummy patterns formed adjacent to the second internal electrodes in the width direction to be spaced apart from the second internal electrodes,

the first dummy patterns are stacked to partially overlap the second internal electrodes, and

the first dummy pattern is formed on only a first side of the first internal electrode in the width direction, the second dummy pattern is formed on only a second side opposite the first side of the second internal electrode in the width direction.

10. The multilayer ceramic capacitor of claim 9 , wherein widths of the first and second internal electrodes are the same as each other.

11. A method of manufacturing a multilayer ceramic capacitor, comprising:

preparing a ceramic green sheet for stacking by printing a conductive metal paste on a ceramic green sheet including a dielectric layer to simultaneously form first and second internal electrodes and a first dummy pattern disposed adjacent to the first internal electrode in a width direction to be spaced apart from the first internal electrode and extending along a length of the first internal electrodes;

forming a laminate by preparing a plurality of ceramic green sheets for stacking and stacking the plurality of ceramic green sheets for stacking so that the first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween and the first dummy patterns partially overlap the second internal electrodes;

preparing a body by compressing, sintering, and cutting the laminate; and

forming first and second external electrodes on end surfaces of the body opposed in a length direction to be electrically connected to the first and second internal electrodes, respectively,

wherein the first dummy pattern is insulated from and not connected to the first and second external electrodes.

12. The method of claim 11 , wherein in the forming of the laminate, the plurality of ceramic green sheets for stacking are stacked so that end portions of the first internal electrodes in the width direction and end portions of the second internal electrodes in the width direction are disposed to be misaligned with each other.

13. The method of claim 11 , wherein in the preparing of the ceramic green sheet for stacking, second dummy patterns are further formed adjacent to the second internal electrodes in the width direction to be spaced apart from the second internal electrodes at the time of printing the conductive metal paste.

14. The method of claim 13 , wherein in the forming of the laminate, the second dummy patterns are stacked to partially overlap the first internal electrodes.

15. The method of claim 11 , wherein the first dummy patterns are not connected to the first and second external electrodes.

16. The method of claim 11 , wherein a thickness of the first dummy pattern is selected to reduce a step portion resulting from a difference between a thickness of the first and second internal electrodes and that of the dielectric layer.

17. A multilayer ceramic capacitor comprising:

a body including dielectric layers and first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween; and

first and second external electrodes disposed on end surfaces of the body opposed in a length direction and connected to the first and second internal electrodes, respectively,

wherein the body includes first dummy patterns formed adjacent to the first internal electrodes in a width direction to be spaced apart from the first internal electrodes and extending along a length of the first internal electrodes, the first dummy patterns being insulated from and not connected to the first and second external electrodes, and

the first dummy patterns are stacked to partially overlap the second internal electrodes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2018
From: HONG, HYUK JIN; KIM, DOO YOUNG; KIM, BYUNG SOO; SUNG, TAE YOUNG; JIN, YOUN SIK
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 044607/0502 →
Priority Claims (1)
KR 10-2017-0124107 · Sep 26, 2017 · national
Continuity (1)
Related Publication 20190096584A1 · Mar 28, 2019
Cited By (1)
US 12,744,156