Multi-threshold voltage semiconductor device

1. A semiconductor device, comprising:

a first metal-oxide semiconductor (MOS) transistor on a substrate;

a first ferroelectric (FE) layer connected to the first MOS transistor, wherein the first FE layer is overlapped by a first gate electrode of the first MOS transistor entirely;

a first buffer layer under and directly contacting the first FE layer, wherein a width of the first FE layer is greater than a width of the first buffer layer;

a second MOS transistor on the substrate;

a second FE layer connected to the second MOS transistor, wherein the first FE layer and the second FE layer comprise different capacitance and different widths and the second FE layer is overlapped by a second gate electrode of the second MOS transistor entirely; and

a second buffer layer under and directly contacting the second FE layer, wherein a width of the second FE layer is greater than a width of the second buffer layer.

2. The semiconductor device of claim 1 , wherein the first MOS transistor comprises:

the first gate electrode on the substrate; and

a first source/drain region adjacent to two sides of the first gate electrode, wherein the second MOS transistor comprises:

the second gate electrode on the substrate; and

a second source/drain region adjacent to two sides of the second gate electrode.

3. The semiconductor device of claim 2 , further comprising:

a first conductor physically contacting the first gate electrode;

a second conductor physically contacting the first source/drain region;

a third conductor physically contacting the second gate electrode; and

a fourth conductor physically contacting the second source/drain region.

4. The semiconductor device of claim 3 , further comprising:

a first metal layer physically contacting the first conductor;

a second metal layer physically contacting the second conductor;

the first FE layer is on the first metal layer;

a third metal layer physically contacting the third conductor;

a fourth metal layer physically contacting the fourth conductor; and

the second FE layer is on the third metal layer.

5. The semiconductor device of claim 4 , wherein the first FE layer and the second FE layer comprise different area.

6. The semiconductor device of claim 4 , wherein the first FE layer and the second FE layer comprise different thickness.

7. The semiconductor device of claim 4 , wherein the first FE layer and the second FE layer comprise different dielectric constant.

8. The semiconductor device of claim 3 , further comprising:

the first FE layer on the first conductor;

a second metal layer physically contacting the second conductor;

a fifth conductor on the first FE layer;

the second FE layer on the third conductor;

a fourth metal layer physically contacting the fourth conductor; and

a sixth conductor on the second FE layer.

9. The semiconductor device of claim 8 , wherein the first FE layer and the second FE layer comprise different area.

10. The semiconductor device of claim 8 , wherein the first FE layer and the second FE layer comprise different thickness.

11. The semiconductor device of claim 8 , wherein the first FE layer and the second FE layer comprise different dielectric constant.

12. The semiconductor device of claim 2 , further comprising:

the first FE layer on the first gate electrode; and

the second FE layer on the second gate electrode.

13. The semiconductor device of claim 12 , wherein the first FE layer and the second FE layer comprise different area.

14. The semiconductor device of claim 12 , wherein the first FE layer and the second FE layer comprise different thickness.

15. The semiconductor device of claim 12 , wherein the first FE layer and the second FE layer comprise different dielectric constant.

16. The semiconductor device of claim 1 , wherein the first MOS transistor and the second MOS transistor comprise different conductive type.