Fuse structure of dynamic random access memory

1. A fuse structure for dynamic random access memory (DRAM), comprising:

a shallow trench isolation (STI) in a substrate;

a first select gate in the substrate and adjacent to one side of the STI;

a second select gate in the substrate and adjacent to another side of the STI; and

a gate structure on the STI, the first select gate, and the second select gate.

2. The fuse structure for DRAM of claim 1 , wherein each of the first select gate and the second select gate comprises:

a barrier layer in the substrate; and

a conductive layer on the barrier layer.

3. The fuse structure for DRAM of claim 2 , further comprising a hard mask on each of the first select gate and the second select gate.

4. The fuse structure for DRAM of claim 3 , wherein a top surface of the hard mask is even with a top surface of the STI.

5. The fuse structure for DRAM of claim 1 , further comprising a doped region between the STI and the first select gate and the second select gate.

6. The fuse structure for DRAM of claim 5 , wherein a bottom surface of the doped region is higher than a top surface of the first select gate.

7. The fuse structure for DRAM of claim 5 , wherein the doped region comprises a n- region.

8. The fuse structure for DRAM of claim 1 , further comprising a spacer around the gate structure and on the first select gate and the second select gate.

9. The fuse structure for DRAM of claim 1 , wherein the gate structure comprises:

a conductive layer;

a metal layer on the conductive layer; and

a mask layer on the metal layer.

10. The fuse structure for DRAM of claim 1 , wherein the gate structure further comprises:

a first gate structure on part of the STI and the first select gate; and

a second gate structure on part of the STI and the second select gate.

11. A fuse structure for dynamic random access memory (DRAM), comprising:

a shallow trench isolation (STI) in a substrate;

a first select gate in the substrate and adjacent to one side of the STI;

a second select gate in the substrate and adjacent to another side of the STI;

a first assist gate in the substrate and between the STI and the first select gate;

a second assist gate in the substrate and between the STI and the second select gate; and

a gate structure on the STI, the first assist gate, and the second assist gate.

12. The fuse structure for DRAM of claim 11 , wherein each of the first select gate, the second select gate, the first assist gate, and the second assist gate comprises:

a barrier layer in the substrate; and

a conductive layer on the barrier layer.

13. The fuse structure for DRAM of claim 12 , further comprising a hard mask on each of the first select gate, the second select gate, the first assist gate, and the second assist gate.

14. The fuse structure for DRAM of claim 13 , wherein a top surface of the hard mask is even with a top surface of the STI.

15. The fuse structure for DRAM of claim 11 , further comprising a doped region between the STI and the first assist gate and the second assist gate.

16. The fuse structure for DRAM of claim 15 , wherein a bottom surface of the doped region is higher than a top surface of the first select gate.

17. The fuse structure for DRAM of claim 15 , wherein the doped region comprises a n- region.

18. The fuse structure for DRAM of claim 11 , further comprising a spacer around the gate structure and on the first assist gate and the second assist gate.

19. The fuse structure for DRAM of claim 11 , wherein the gate structure comprises:

a conductive layer;

a metal layer on the conductive layer; and

a mask layer on the metal layer.

20. The fuse structure for DRAM of claim 11 , wherein the gate structure further comprises:

a first gate structure on part of the STI and the first assist gate; and

a second gate structure on part of the STI and the second assist gate.