Vertical gate-all-around transistor and manufacturing method thereof

1. A semiconductor device, comprising:

an isolation structure, disposed on a substrate, wherein the isolation structure comprises:

a main portion, blanketing the substrate; and

a protrusion portion, protruding vertically from a top surface of the main portion, wherein the protrusion portion is an air gap and the main portion comprises a dielectric material;

an outer structure, surrounding the protrusion portion of the isolation structure, wherein the outer structure is in direct contact with the protrusion portion and the outer structure is separated from the substrate by the main portion;

wherein a material of the outer structure comprises a metal chalcogenide 2D material; and

a gate structure, surrounding a central part of the outer structure, such that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.

2. The semiconductor device of claim 1 , wherein the isolation structure is perpendicular to a top surface of the substrate to form a vertical nanowire structure.

3. The semiconductor device of claim 1 , wherein the dielectric material comprises silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material with a dielectric constant below 4.

4. The semiconductor device of claim 1 , wherein the metal chalcogenide 2D material comprises metal atoms of one of Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge, and Pb and chalcogen atoms of one of S, Se, and Te.

5. The semiconductor device of claim 1 , wherein a conductivity type of the channel region, a conductivity type of the source region, and a conductivity type of the drain region are the same.

6. The semiconductor device of claim 1 , wherein a conductivity type of the source region and a conductivity type of the drain region are the same, while the conductivity type of the source region and the conductivity type of the drain region are different from a conductivity type of the channel region.

7. The semiconductor device of claim 1 , wherein the protrusion portion comprises a plurality of protrusion portions, and a diameter of one of the plurality of protrusion portions is the same as a diameter of another of the plurality of protrusion portions.

8. The semiconductor device of claim 1 , wherein the protrusion portion comprises a plurality of protrusion portions, and a diameter of one of the plurality of protrusion portions is different from a diameter of another of the plurality of protrusion portions.

9. The semiconductor device of claim 1 , wherein the gate structure comprises a gate dielectric layer and a gate electrode, and the gate dielectric layer is located between the gate electrode and the channel region.

10. A method of fabricating a semiconductor device, comprising:

forming an isolation structure on a substrate, wherein the isolation structure comprises:

a main portion, blanketing the substrate, wherein the main portion comprises a dielectric material; and

a protrusion portion, protruding vertically from a top surface of the main portion;

forming an outer structure on a sidewall of the protrusion portion of the isolation structure;

wherein a material of the outer structure comprises a metal chalcogenide 2D material;

forming a sacrificial layer on the substrate, the sacrificial layer surrounding a lower part the outer structure;

forming a gate structure on the sacrificial layer, the gate structure surrounding a central part of the outer structure, such that the central part covered by the gate structure becomes a channel region, and the lower part and an upper part of the outer structure respectively become a source region and a drain region;

removing the sacrificial layer;

forming a dielectric layer on the substrate to cover the gate structure and the outer structure;

patterning the dielectric layer to expose a top surface of the protrusion portion of the isolation structure;

removing the protrusion portion of the isolation structure to form an air gap on the main portion; and

sealing the air gap, wherein the outer structure is in direct contact with the air gap and the outer structure is separated from the substrate by the main portion.

11. The method of fabricating the semiconductor device of claim 10 , wherein the forming the isolation structure on the substrate comprises:

sequentially forming an isolation structure material and a mask pattern on the substrate;

removing a part of the isolation structure material with use of the mask pattern as a mask; and

performing a rounding process on a remainder part of the isolation structure material.

12. The method of fabricating the semiconductor device of claim 11 , wherein the rounding process comprises a standard clean 1 process, a cleaning process containing dilute hydrofluoric acid, or a combination thereof.

13. The method of fabricating the semiconductor device of claim 11 , wherein the forming the outer structure on the sidewall of the protrusion portion of the isolation structure comprises:

conformally forming a seed layer on the isolation structure after performing the rounding process;

epitaxially growing a channel material on the seed layer; and

etching back the seed layer and the channel material to expose a top surface of the mask pattern.

14. The method of fabricating the semiconductor device of claim 10 , wherein a material of the sacrificial layer comprises: silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof.