Electronic device

1. An electronic device, comprising:

a first chip including a first conductive member, a first region, and a second region;

a second chip including a second conductive member, a third region, and a fourth region;

a third chip including a third conductive member, a fifth region, and a sixth region;

a first terminal;

a second terminal; and

an interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip,

the interconnect layer including

a fourth conductive member provided between the first region of the first chip and the third region of the second chip, the fourth conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip, and

a fifth conductive member provided between the second region of the first chip and the fifth region of the third chip, the fifth conductive member connecting the first conductive member of the first chip and the third conductive member of the third chip,

the first chip being provided between the first terminal and the second terminal, and being an electrical interconnect member connecting the second chip and the third chip via the first conductive member, the fourth conductive member, and the fifth conductive member.

2. The device according to claim 1 , wherein the first chip does not include a substrate.

3. The device according to claim 1 , wherein the third chip includes a memory element.

4. The device according to claim 1 , wherein the first chip further includes a first memory element connected to the fourth conductive member.

5. The device according to claim 4 , wherein the third chip further includes a second memory element connected to the fifth conductive member.

6. The device according to claim 5 , wherein a memory capacity of the second memory element is larger than a memory capacity of the first memory element.

7. The device according to claim 5 , wherein the first chip further includes a controller connected to the fifth conductive member.

8. The device according to claim 1 , wherein

the second chip further includes a first power supply terminal,

the third chip further includes a second power supply terminal, and

the interconnect layer further includes a sixth conductive member and a seventh conductive member, the sixth conductive member connecting the first power supply terminal and the first terminal, the seventh conductive member connecting the second power supply terminal and the second terminal.

9. The device according to claim 8 , wherein

the interconnect layer further includes an insulating layer provided between the fourth conductive member and the sixth conductive member, and between the fifth conductive member and the seventh conductive member,

the fourth conductive member and the sixth conductive member are insulatively separated, and

the fifth conductive member and the seventh conductive member are insulatively separated.

10. An electronic device, comprising:

a first chip including a first conductive member, a first region, and a second region;

a second chip including a second conductive member, a third region, and a fourth region;

a third chip including a third conductive member, a fifth region, and a sixth region;

a first terminal;

a second terminal; and

an interconnect layer provided between the first region of the first chip and the third region of the second chip, between the second region of the first chip and the fifth region of the third chip, between the first terminal and the fourth region of the second chip, and between the second terminal and the sixth region of the third chip,

the interconnect layer including

a fourth conductive member provided between the first region of the first chip and the third region of the second chip, the fourth conductive member connecting the first conductive member of the first chip and the second conductive member of the second chip, and

a fifth conductive member provided between the second region of the first chip and the fifth region of the third chip, the fifth conductive member connecting the first conductive member of the first chip and the third conductive member of the third chip,

the first chip being provided between the first terminal and the second terminal, and including a first memory element connected to the fourth conductive member, and

the third chip including a second memory element connected to the fifth conductive member.

11. The device according to claim 10 , wherein a memory capacity of the second memory element is larger than a memory capacity of the first memory element.

12. The device according to claim 10 , wherein the first chip further includes a controller connected to the fifth conductive member.

13. The device according to claim 10 , wherein

the second chip further includes a first power supply terminal,

the third chip further includes a second power supply terminal, and

the interconnect layer further includes a sixth conductive member and a seventh conductive member, the sixth conductive member connecting the first power supply terminal and the first terminal, the seventh conductive member connecting the second power supply terminal and the second terminal.

14. The device according to claim 13 , wherein

the interconnect layer further includes an insulating layer provided between the fourth conductive member and the sixth conductive member, and between the fifth conductive member and the seventh conductive member,

the fourth conductive member and the sixth conductive member are insulatively separated, and

the fifth conductive member and the seventh conductive member are insulatively separated.