IP Library › Granted Patent US 10,475,794
Granted Patent B1
US 10,475,794 · App. 16/026,069 · Granted Nov 12, 2019

Semiconductor device and method for fabricating the same

Inventors: Po-Han Wu (Pingtung County, TW); Fu-Che Lee (Taichung, TW); Chien-Cheng Tsai (Kaohsiung, TW); Tzu-Tsen Liu (Kaohsiung, TW); Wen-Chieh Lu (Taoyuan, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10805H01L21/762H01L27/10885H01L27/10888H01L27/10891
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Quick Facts
Patent No.
US 10,475,794
App. No.
16/026,069
Granted
Nov 12, 2019
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.

Claims (30)

1. A method for fabricating semiconductor device, comprising:

forming a first bit line structure on a substrate;

forming a first spacer adjacent to the first bit line structure;

forming an interlayer dielectric (ILD) layer adjacent to the first spacer;

removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and

forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.

2. The method of claim 1 , further comprising:

forming the first bit line structure and a second bit line structure on the substrate;

forming the first spacer adjacent to the first bit line structure and a second spacer adjacent to the second bit line structure;

forming the ILD layer between the first spacer and the second spacer;

removing part of the ILD layer, part of the first spacer, and part of the second spacer to expose a sidewall of the first bit line structure and a sidewall of the second bit line structure; and

forming the first storage node contact isolation structure between the first bit line structure and the second bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure, the first spacer, the second bit line structure and the second spacer directly.

3. The method of claim 2 , further comprising forming the first storage node contact isolation structure and a second storage node contact isolation structure between the first bit line structure and the second bit line structure.

4. The method of claim 3 , wherein the second storage node contact isolation structure contacts the first bit line structure, the first spacer, the second bit line structure and the second spacer directly.

5. The method of claim 3 , further comprising forming a storage node contact between the first storage node contact isolation structure and the second storage node contact isolation structure.

6. The method of claim 5 , wherein the storage node contact contacts the first spacer, the second spacer, the first storage node contact isolation structure, and the second storage node contact isolation structure directly.

7. The method of claim 1 , wherein the first storage node contact isolation structure comprises silicon carbon nitride (SiCN).

8. A semiconductor device, comprising:

a first bit line structure extending along a first direction on a substrate;

a first spacer extending along the first direction adjacent to the first bit line structure; and

a first storage node contact isolation structure extending along a second direction adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.

9. The semiconductor device of claim 8 , further comprising:

a second bit line structure extending along the first direction on the substrate;

a second spacer extending along the first direction adjacent to the second bit line structure; and

the first storage node contact isolation structure between the first bit line structure and the second bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure, the first spacer, the second bit line structure, and the second spacer directly.

10. The semiconductor device of claim 9 , further comprising a second storage node contact isolation structure between the first bit line structure and the second bit line structure.

11. The semiconductor device of claim 10 , wherein the second storage node contact isolation structure contacts the first bit line structure, the first spacer, the second bit line structure and the second spacer directly.

12. The semiconductor device of claim 10 , further comprising a storage node contact between the first storage node contact isolation structure and the second storage node contact isolation structure.

13. The semiconductor device of claim 12 , wherein the storage node contact contacts the first spacer, the second spacer, the first storage node contact isolation structure, and the second storage node contact isolation structure directly.

14. The semiconductor device of claim 8 , wherein the first storage node contact isolation structure comprises silicon carbon nitride (SiCN).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2018
From: WU, PO-HAN; LEE, FU-CHE; TSAI, CHIEN-CHENG; LIU, TZU-TSEN; LU, WEN-CHIEH
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046263/0676 →
Priority Claims (1)
CN 2018 1 0582040 · Jun 7, 2018 · national
Cited By (2)
US 12,237,215 US 12,512,374