IC including standard cells and SRAM cells
An IC is provided. The IC includes a plurality of P-type fin field-effect transistors (FinFETs). At least one first P-type FinFET includes a silicon germanium (SiGe) channel region. At least one second P-type FinFET includes a Si channel region. Source and drain regions of the plurality of P-type FinFETs include SiGe and a p-type impurity.
1. An integrated circuit (IC), comprising:
a plurality of standard cells, wherein P-type fin field-effect transistors (FinFETs) of the plurality of standard cells share a first semiconductor fin including silicon germanium (SiGe); and
a plurality of SRAM cells, wherein P-type FinFETs of two adjacent SRAM cells share a second semiconductor fin including Si,
wherein source and drain regions of the P-type FinFETs of the standard cells and the SRAM cells comprise SiGe and a p-type impurity,
wherein a length of the second semiconductor fin is shorter than a length of the first semiconductor fin.
2. The IC as claimed in claim 1 , wherein in the standard cell, the source and drain regions of the P-type FinFET extending from the first semiconductor fin of the P-type FinFET comprise a doping layer including SiGe and Boron, and the width of the doping layer is wider than that of a channel region in the P-type FinFET.
3. The IC as claimed in claim 2 , wherein in the standard cell, Ge atomic concentration in the channel region of the P-type FinFET is in a range from about 10% to about 40%.
4. The IC as claimed in claim 1 , wherein in the SRAM cell, the source and drain regions of the P-type FinFET extending from the second semiconductor fin of the P-type FinFET comprise a doping layer including SiGe and Boron, and width of the doping layer is wider than that of a channel region of the P-type FinFET.
5. The IC as claimed in claim 1 , wherein Ge atomic concentration in the source and drain regions of the P-type FinFETs of the standard cells and the SRAM cells is in a range from about 30% to about 75%.
6. The IC as claimed in claim 1 , wherein the number of P-type FinFETs of the plurality of standard cells that share the first semiconductor fin is greater than or equal to 3.
7. An integrated circuit (IC), comprising:
a plurality of standard cells, wherein P-type fin field-effect transistors (FinFETs) of the plurality of standard cells share a first semiconductor fin including a first material, and N-type FinFETs of the plurality of standard cells share a second semiconductor fin including a second material that is different from the first material; and
a plurality of SRAM cells, wherein P-type FinFETs of two adjacent SRAM cells share a third semiconductor fin including a third material different from the first material, and N-type FinFETs of the plurality of SRAM cells share a fourth semiconductor fin including the second material,
wherein the first material comprises silicon germanium (SiGe),
wherein a first length of the first semiconductor fin is equal to a second length of the second semiconductor fin, and a third length of the third semiconductor fin is shorter than a fourth length of the fourth semiconductor fin.
8. The IC as claimed in claim 7 , wherein in the standard cell, source and drain regions of the P-type FinFET extending from the first semiconductor fin of the P-type FinFET comprise a doping layer including SiGe and Boron, and width of the doping layer is wider than that of channel region of the P-type FinFET.
9. The IC as claimed in claim 8 , wherein in the standard cell, Ge atomic concentration in the channel region of the P-type FinFET is in a range from about 10% to about 40%.
10. The IC as claimed in claim 7 , wherein in the SRAM cell, source and drain regions of the P-type FinFET extending from the third semiconductor fin of the P-type FinFET comprise a doping layer including SiGe and Boron, and width of the doping layer is wider than that of channel region of the P-type FinFET.
11. The IC as claimed in claim 7 , wherein Ge atomic concentration in source and drain regions of the P-type FinFETs of the standard cells and the SRAM cells is in a range from about 30% to about 75%.
12. The IC as claimed in claim 7 , wherein source and drain regions of the plurality of P-type FinFETs comprise SiGe and a p-type impurity, and the number of P-type FinFETs of the plurality of standard cells that share the first semiconductor fin is greater than or equal to 3.
13. An integrated circuit (IC), comprising:
a plurality of P-type fin field-effect transistors (FinFETs), comprising:
at least one first P-type FinFET comprising a silicon germanium (SiGe) channel region; and
at least one second P-type FinFET comprising a Si channel region, wherein source and drain regions of the plurality of P-type FinFETs comprise SiGe and a p-type impurity;
at least one standard cell comprising the first P-type FinFET; and
at least one SRAM memory cell comprising the second P-type FinFET.
14. The IC as claimed in claim 13 , wherein in the standard cell, a sidewall depth of the SiGe channel region of the P-type FinFETs is in a range from about 35 nm to about 90 nm.
15. The IC as claimed in claim 13 , wherein the source and drain regions of the first P-type FinFET extending from the SiGe channel region of the first P-type FinFET comprise a doping layer including SiGe and Boron, and width of the doping layer is wider than that of the SiGe channel region of the first P-type FinFET.
16. The IC as claimed in claim 15 , wherein in the first P-type FinFET, Ge atomic concentration in the SiGe channel region is in a range from about 10% to about 40% and is less than Ge atomic concentration in the doping layer.
17. The IC as claimed in claim 13 , wherein the source and drain regions of the second P-type FinFET extending from the Si channel region of the second P-type FinFET comprise a doping layer including SiGe and Boron, and width of the doping layer is wider than that of the Si channel region of the second P-type FinFET.
18. The IC as claimed in claim 13 , wherein Ge atomic concentration in the source and drain regions of the plurality of P-type FinFETs is in a range from about 30% to about 75%.
19. The IC as claimed in claim 13 , further comprising:
a plurality of N-type FinFETs,
wherein each of the plurality of N-type FinFET comprises a Si channel region, and source and drain regions of the N-type FinFET comprise SiP, SiC, SiPC, SiAs, Si, or a combination thereof.
20. The IC as claimed in claim 13 , wherein channel width of the Si channel region of the second P-type FinFET is narrower than channel width of the SiGe channel region of the first P-type FinFET.