Ferroelectric memory device and method of manufacturing the same

1. A ferroelectric memory device comprising:

a substrate having a source region and a drain region;

a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked;

a depolarization suppressing layer disposed on the ferroelectric superlattice;

a gate electrode layer disposed on the depolarization suppressing layer,

wherein each of the at least two kinds of different dielectric layers is a monolayer,

wherein the depolarization suppressing layer has a non-ferroelectric property and includes a layer with substantially the same composition as one of at least two kinds of different dielectric layers,

wherein the depolarization suppressing layer disposed between the superlattice structure and the gate electrode layer comprises a zirconium oxide layer or an aluminum oxide layer.

2. The ferroelectric memory device of claim 1 ,

wherein the superlattice structure comprises a hafnium oxide layer and a zirconium oxide layer.

3. The ferroelectric memory device of claim 2 ,

wherein the hafnium oxide layer and the zirconium oxide layer have substantially the same thickness.

4. The ferroelectric memory device of claim 1 ,

wherein the superlattice structure comprises a plurality of unit-stack structures, and

each unit-stack in the plurality of unit-stack structures comprises one hafnium oxide layer and one zirconium oxide layer.

5. The ferroelectric memory device of claim 4 ,

wherein an uppermost layer of the superlattice structure comprises a hafnium oxide layer.

6. The ferroelectric memory device of claim 4 ,

wherein the superlattice structure has a total thickness of about 5 nm to 20 nm.

7. The ferroelectric memory device of claim 1 ,

wherein the gate electrode layer comprises at least one selected from tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide and ruthenium oxide.

8. The ferroelectric memory device of claim 1 ,

further comprising an interfacial insulation layer disposed between the substrate and the superlattice structure,

wherein the interfacial insulation layer comprises one selected from silicon oxide, silicon nitride and silicon oxynitride.

9. A method of manufacturing a ferroelectric memory device comprising:

providing a substrate;

forming a ferroelectric superlattice structure by alternately stacking at least two kinds of different dielectric layers on the substrate;

forming a depolarization suppressing layer with a non-ferroelectric property on the ferroelectric superlattice structure;

forming a gate electrode layer on the depolarization suppressing layer, wherein each of the at least two kinds of different dielectric layers is a monolayer,

wherein the depolarization suppressing layer includes a layer with substantially the same composition as one of at least two kinds of different dielectric layers,

wherein the depolarization suppressing layer between the superlattice structure and the gate electrode layer-comprises an aluminum oxide layer.

10. The method of claim 9 ,

wherein forming the superlattice structure is performed using one of an atomic layer deposition method, a chemical vapor deposition method, a molecular beam deposition method and an evaporation method.

11. The method of claim 9 ,

wherein forming the superlattice structure is performed at a substrate temperature of 150° C. to 350° C.

12. The method of claim 9 ,

wherein forming the superlattice structure comprises:

forming at least one hafnium oxide layer as a monolayer; and

forming at least one zirconium oxide layer as a monolayer in contact with the at least one hafnium oxide layer,

wherein the thickness of each hafnium oxide layer and the thickness of each zirconium oxide layer are substantially the same.

13. The method of claim 12 , wherein in forming the superlattice structure, a total thickness of the superlattice structure is about to 5 nm to 20 nm.

14. The method of claim 12 , wherein in forming the superlattice structure, the hafnium oxide layer is formed as the uppermost layer of the superlattice structure.

15. The method of claim 9 , wherein the gate electrode layer comprises at least one selected from tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide and ruthenium oxide.

16. The method of claim 9 ,

further comprising performing a crystallization heat treatment on the superlattice structure,

wherein the crystallization heat treatment is performed at a process temperature of 400° C. to 600° C.

17. The method of claim 16 ,

wherein the crystallization heat treatment is performed during formation of the gate electrode layer.