Pillar contact extension and method for producing the same

1. A method comprising:

forming a photoresist layer over a first low-K layer formed over an interlayer dielectric (ILD) having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region;

forming a trench through the photoresist layer over each pillar-shaped conductor;

extending the trench through the first low-K layer to an upper surface of each pillar-shaped conductor;

forming a second metal layer over the first low-K layer, filling the trench entirely;

planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor;

forming the photoresist layer over an oxide layer formed over the first low-K layer;

extending the trench through the oxide layer;

forming the second metal layer over the oxide layer;

planarizing the second metal layer until the second metal layer and the oxide layer are removed from over the logic region;

forming a nitride floating cap (NFC) layer and a low temperature oxide (LTO) layer over the first low-K layer prior to forming the photoresist layer; and

forming the trench through the NFC layer and the LTO layer.

2. The method according to claim 1 , comprising planarizing the second metal layer by:

chemical-mechanical planarization (CMP) with dishing.

3. The method according to claim 2 , wherein the CMP is highly selective to the second metal layer compared to the first low-K layer.

4. The method according to claim 1 , wherein a pillar-shaped conductor comprises a metal tunnel junction (MTJ) structure.

5. The method according to claim 1 , further comprising;

forming a second low-K layer over the first low-K layer and the second metal layer; and

forming a BEOL contact down to at least each pillar contact extension in the memory region and the first metal layer in the logic region through the second low-K layer and the first low-K layer, respectively.

6. A device comprising:

an interlayer dielectric (ILD) with a memory region and a logic region;

a metal layer in the memory region and in the logic region;

pillar-shaped conductors over the metal layer only in the memory region;

a pillar contact extension atop of each pillar-shaped conductor;

a first low-K layer over the metal layer and the ILD and surrounding each pillar contact extension, the first low-K layer over the memory region and an upper surface of each pillar contact extension being coplanar;

a second low-K layer over the first low-K layer and pillar contact extensions; and

a BEOL contact at least atop of each pillar contact extension in the memory region and the metal layer in the logic region and through the second low-K layer and the first low-K layer, respectively.

7. The device according to claim 6 , wherein the metal layer comprises copper (Cu), the device further comprising:

a capping layer over the ILD and a portion of the metal layer in the memory region and a portion of the metal layer in the logic region.

8. The device according to claim 7 , further comprising:

a second capping layer over a remaining portion of the metal layer in the logic region.

9. The device according to claim 8 , further comprising:

an oxide layer over the capping layer and the second capping layer; and

a silicon nitride (SiN) layer over the oxide layer.

10. The device according to claim 7 , further comprising:

an oxide layer over the capping layer; and

a SiN layer over the oxide layer.

11. The device according to claim 7 , wherein the pillar-shaped conductor comprises a magnetic tunnel junction (MTJ) structure and a metal-filled via.

12. The device according to claim 11 , wherein the pillar-shaped conductor comprises the MTJ structure and the metal-filled via, the device further comprising:

a SiN layer along sidewalls of each MTJ structure.

13. The device according to claim 6 , wherein the pillar contact extension comprises tantalum nitride (TaN).

14. A method comprising:

forming a photoresist layer over an oxide layer formed over a first low-K layer formed over an interlayer dielectric (ILD) having a copper (Cu) layer in a memory region and in a logic region and metal tunnel junction (MTJ) structures formed atop of the Cu layer only in the memory region;

forming a trench through the photoresist layer down to the oxide layer over each MTJ;

extending the trench through the oxide layer and the first low-K layer down to an upper surface of each MTJ;

forming a tantalum nitride (TaN) layer over the first low-K layer, filling the trench entirely;

chemical-mechanical planarizing (CMP) the TaN layer until the TaN layer and the oxide layer are removed from over the logic region, a TaN pillar contact extension formed atop of each MTJ;

forming a second low-K layer over the TaN layer and the first low-K layer; and

forming a back-end-of-line (BEOL) contact down to at least each TaN pillar contact extension in the memory region and the Cu layer in the logic region through the second low-K layer and the first low-K layer, respectively.

15. The method according to claim 14 , comprising forming the first low-K layer and the second low-K layer of a hydrogenated oxidized silicon carbon (SiCOH) dielectric film or a similar ILD material.

16. The method according to claim 14 , further comprising:

forming a nitride floating cap (NFC) layer and a low temperature oxide (LTO) layer over the oxide layer prior to forming the photoresist layer; and

forming the trench through the NFC layer and the LTO layer.

17. The method according to claim 14 , wherein the CMP is highly selective to the TaN layer compared to the first low-K layer.