IP Library › Granted Patent US 10,481,283
Granted Patent B2
US 10,481,283 · App. 16/181,386 · Granted Nov 19, 2019

Configurable analog-to-digital converter and processing for photon counting

Inventors: Rakul Viswanath (Chennai, IN); Nagesh Surendranath (Bengaluru, IN); Goli Sravana Kumar (Bengaluru, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
G01T1/247G01T1/17H03M1/46
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Quick Facts
Patent No.
US 10,481,283
App. No.
16/181,386
Granted
Nov 19, 2019
Kind
B2
Abstract

A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.

Claims (20)

1. A photon counting system, comprising:

a photon sensor;

a charge sensitive amplifier (CSA) coupled to the photon sensor; and

an analog to digital converter (ADC) coupled to the CSA, the ADC comprising:

successive approximation circuitry comprising:

an N-bit digital-to-analog converter (DAC);

an N-bit successive approximation register (SAR);

a plurality of N-bit registers;

a multiplexer.

2. The photon counting system of claim 1 , wherein each of the N-bit registers is representative of an energy value corresponding to an energy bin of the photon counting system.

3. The photon counting system of claim 1 , wherein the ADC comprises a mode selection input for reception of a signal that controls whether the multiplexer routes outputs of the SAR or the N-bit registers to the DAC.

4. An analog to digital converter (ADC), comprising:

successive approximation circuitry comprising:

an N-bit digital-to-analog converter (DAC);

an N-bit successive approximation register (SAR) coupled to the DAC;

a plurality (M) of N-bit registers coupled to a multiplexer;

wherein the multiplexer is coupled to the DAC and SAR.

5. The ADC of claim 4 , further comprising:

a mode selection input; and

control circuitry coupled to the mode selection input.

Continuity (2)
Continuation 15667445 · Aug 2, 2017
Related Publication 20190086561A1 · Mar 21, 2019