IP Library Granted Patent US 10,482,941
Granted Patent B2
US 10,482,941 · App. 16/128,554 · Granted Nov 19, 2019

Magnetic memory device

Inventors: Takuya Shimada (Tokyo, JP); Yasuaki Ootera (Kanagawa, JP); Tsuyoshi Kondo (Kanagawa, JP); Nobuyuki Umetsu (Kanagawa, JP); Michael Arnaud Quinsat (Kanagawa, JP); Masaki Kado (Kanagawa, JP); Susumu Hashimoto (Tokyo, JP); Shiho Nakamura (Kanagawa, JP); Hideaki Aochi (Mie, JP); Tomoya Sanuki (Mie, JP); Shinji Miyano (Kanagawa, JP); Yoshihiro Ueda (Kanagawa, JP); Yuichi Ito (Mie, JP); Yasuhito Yoshimizu (Mie, JP)
Assignee: Toshiba Memory Corporation
G11C11/1675G11C11/161G11C11/1673H01F10/3254H01L27/228H01L43/02G11C11/02G11C11/16
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Quick Facts
Patent No.
US 10,482,941
App. No.
16/128,554
Granted
Nov 19, 2019
Kind
B2
Abstract

According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.

Claims (61)

1. A magnetic memory device, comprising:

a first memory portion including

a first magnetic portion including a first portion and a second portion,

a first magnetic layer, and

a first nonmagnetic layer provided between the second portion and the first magnetic layer;

a first conductive portion electrically connected to the first portion;

a first interconnection electrically connected to the first magnetic layer; and

a controller electrically connected to the first conductive portion and the first interconnection,

the controller being configured to apply a first pulse between the first conductive portion and the first interconnection in a first write operation, the first pulse having a first pulse height and a first pulse length,

the controller being configured to apply a second pulse between the first conductive portion and the first interconnection in a first shift operation, the second pulse having a second pulse height and a second pulse length,

an absolute value of the second pulse height being less than an absolute value of the first pulse height,

the second pulse length being longer than the first pulse length.

2. The device according to claim 1 , wherein

the controller applies a third pulse between the first conductive portion and the first interconnection in a first read operation, the third pulse having a third pulse height and a third pulse length, and

an absolute value of the third pulse height is less than the absolute value of the second pulse height.

3. The device according to claim 2 , further comprising a first switch provided in a first current path between the first conductive portion and the first interconnection,

the third pulse being supplied to the first memory portion via the first switch.

4. The device according to claim 1 , further comprising a first switch provided in a first current path including the first conductive portion, the first memory portion, and the first interconnection,

the first pulse and the second pulse being supplied to the first memory portion via the first switch.

5. The device according to claim 4 , further comprising a second interconnection electrically connected to a first gate of the first switch.

6. The device according to claim 4 , further comprising:

a second memory portion; and

a second switch,

the second memory portion including

a second magnetic portion including a third portion and a fourth portion,

a second magnetic layer, and

a second nonmagnetic layer provided between the fourth portion and the second magnetic layer,

the second switch being provided in a second current path including the second memory portion and the first interconnection,

the controller switching the first switch ON and switching the second switch OFF in the first write operation,

the controller switching the first switch ON and switching the second switch OFF in the first shift operation.

7. The device according to claim 6 , further comprising a third interconnection electrically connected to a second gate of the second switch.

8. The device according to claim 6 , wherein

the controller switches the first switch OFF and switches the second switch ON in a second write operation, and

the controller switches the first switch OFF and switches the second switch ON in a second shift operation.

9. The device according to claim 1 , wherein

the first magnetic portion has a tubular configuration extending along a first direction,

the first magnetic portion has a first surface on an outer side, and

a position of the first surface in a second direction changes periodically along the first direction, the second direction crossing the first direction.

10. The device according to claim 1 , wherein

the first magnetic portion has a tubular configuration extending along a first direction,

the first magnetic portion has a second surface on an inner side, and

a position of the second surface in a second direction changes periodically along the first direction, the second direction crossing the first direction.

11. The device according to claim 1 , wherein

the first pulse is positive when writing first information in the first write operation, and

in the first write operation, the first pulse is negative when writing second information different from the first information.

12. The device according to claim 1 , wherein

the second pulse is positive when shifting information in a first orientation in the first shift operation, and

the second pulse is negative when shifting the information in a second orientation in the first shift operation, the second orientation being the reverse of the first orientation.

13. The device according to claim 1 , wherein

the first magnetic portion includes a domain wall, and

a position of the domain wall is different before and after the applying of the second pulse.

14. The device according to claim 1 , wherein

in the first write operation, the controller applies a first prepulse between the first conductive portion and the first interconnection before the applying of the first pulse, the first prepulse having a first prepulse height and a first prepulse length,

an absolute value of the first prepulse height is less than the absolute value of the first pulse height,

the first prepulse length is longer than the first pulse length, and

a polarity of the first prepulse is the reverse of a polarity of the first pulse.

15. The device according to claim 14 , wherein the first prepulse length is not less than 0.2 times but less than 1 times the second pulse length.

16. The device according to claim 14 , wherein the first prepulse length is 0.5 times the second pulse length or less.

17. The device according to claim 1 , wherein

the absolute value of the second pulse height is ½ of the absolute value of the first pulse height or less, and

the second pulse length is 2 times the first pulse length or more.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2018
From: SHIMADA, TAKUYA; OOTERA, YASUAKI; KONDO, TSUYOSHI; UMETSU, NOBUYUKI; QUINSAT, MICHAEL ARNAUD; KADO, MASAKI; HASHIMOTO, SUSUMU; NAKAMURA, SHIHO; AOCHI, HIDEAKI; SANUKI, TOMOYA; MIYANO, SHINJI; UEDA, YOSHIHIRO; ITO, YUICHI; YOSHIMIZU, YASUHITO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 047429/0452 →
Priority Claims (1)
JP 2018-047148 · Mar 14, 2018 · national
Continuity (1)
Related Publication 20190287598A1 · Sep 19, 2019