IP Library › Granted Patent US 10,483,115
Granted Patent B2
US 10,483,115 · App. 15/692,528 · Granted Nov 19, 2019

Semiconductor device and method for manufacturing the same

Inventors: You-Hua Chou (Hsinchu, TW); Kuo-Sheng Chuang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L21/28556H01L21/76843H01L21/76876H01L21/76879H01L23/528H01L23/5226H01L23/5328H01L23/53276H01L23/585
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,483,115
App. No.
15/692,528
Granted
Nov 19, 2019
Kind
B2
Abstract

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.

Claims (48)

1. A semiconductor device, comprising:

a non-insulator structure formed in one of a source/drain region and a gate structure;

at least one carbon nano-tube (CNT) over the non-insulator structure;

a dielectric layer surrounding the CNT; and

a graphene-based conductive layer over the at least one CNT.

2. The semiconductor device of claim 1 , further comprising:

a conductive material filling interspaces between a plurality of the at least one CNTs.

3. The semiconductor device of claim 2 , wherein the non-insulator structure comprises a metal silicide, and the metal silicide and the conductive material comprise the same metal.

4. The semiconductor device of claim 1 , further comprising:

a catalyst layer between the at least one CNT and the non-insulator structure.

5. The semiconductor device of claim 4 , wherein the catalyst layer and the non-insulator structure comprise the same metal.

6. The semiconductor device of claim 1 , further comprising:

a catalyst layer between the graphene-based conductive layer and the at least one CNT.

7. The semiconductor device of claim 6 , wherein the catalyst layer wraps around the graphene-based conductive layer.

8. The semiconductor device of claim 1 , further comprising:

a conductor, wherein the graphene-based conductive layer wraps around the conductor.

9. The semiconductor device of claim 8 , wherein a top surface of the conductor is substantially level with an end surface of the graphene-based conductive layer.

10. A semiconductor device, comprising:

a non-insulator structure;

a carbon nano-tube (CNT) electrically connected to the non-insulator structure;

a first dielectric layer, the CNT being within the first dielectric layer;

a second dielectric layer over the first dielectric layer; and

a U-shaped graphene-based conductive layer within the second dielectric layer and electrically connected to the CNT.

11. The semiconductor device of claim 10 , further comprising:

a first catalyst layer; and

a second catalyst layer, wherein the CNT is in between the first catalyst layer and the second catalyst layer.

12. The semiconductor device of claim 11 , wherein the CNT is in contact with the first catalyst layer.

13. The semiconductor device of claim 11 , wherein the U-shaped graphene-based conductive layer is in contact with the second catalyst layer.

14. The semiconductor device of claim 11 , further comprising:

a metal wrapping around the CNT.

15. The semiconductor device of claim 11 , further comprising:

a metal, wherein the U-shaped graphene-based conductive layer is disposed on sidewalls and a bottom surface of the metal.

16. A method for manufacturing a semiconductor device, comprising:

forming a hole in a first dielectric layer over a non-insulator structure;

forming a carbon nano-tube (CNT) in the hole and electrically connected to the non-insulator structure;

forming a second dielectric layer over the CNT and the first dielectric layer;

forming a trench in the second dielectric layer and exposing a top surface of the CNT; and

after forming the trench, forming a graphene-based conductive layer in the trench and electrically connected to the CNT.

17. The method of claim 16 , wherein the forming the CNT comprises:

forming a catalyst layer in the hole; and

growing the CNT over the catalyst layer.

18. The method of claim 16 , further comprising:

filling the hole with a metal after the forming the CNT.

19. The method of claim 16 , wherein the forming the graphene-based conductive layer comprises:

forming a catalyst layer in the trench; and

growing the graphene-based conductive layer over the catalyst layer.

20. The method of claim 16 , further comprising:

filling the trench with a metal after the forming the graphene-based conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2017
From: CHOU, YOU-HUA; CHUANG, KUO-SHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 043467/0612 →
Continuity (2)
Provisional Application 62489444 · Apr 24, 2017
Related Publication 20180308702A1 · Oct 25, 2018