Logic cell structure with interconnection design and configuration
The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P 1 ; the second metal lines have a second pitch P 2 ; the third metal lines have a third pitch P 3 ; and the gates have a fourth pitch P 4 , wherein a ratio of the second pitch over the fourth pitch P 2 :P 4 is about 3:2.
1. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
the first metal lines have a first pitch P 1 ;
the second metal lines have a second pitch P 2 ;
the third metal lines have a third pitch P 3 ; and
the gates have a fourth pitch P 4 , wherein a ratio of the second pitch over the fourth pitch P 2 :P 4 is about 3:2.
2. The semiconductor structure of claim 1 , wherein the plurality of FETs include an n-type conductivity field-effect transistor (nFET) and a p-type conductivity field-effect transistor (pFET) coupled together to form an inverter, wherein the inverter spans a dimension of about 2*P 4 along the second direction.
3. The semiconductor structure of claim 1 , wherein the plurality of FETs are configured to an NAND gate spanning a dimension of about 3*P 4 along the second direction.
4. The semiconductor structure of claim 1 , wherein the plurality of FETs are configured to an NOR gate spanning a dimension of about 3*P 4 along the second direction.
5. The semiconductor structure of claim 1 , wherein the second pitch P 2 is less than the first pitch P 1 and the third pitch P 3 .
6. The semiconductor structure of claim 1 , wherein the first metal lines have a first thickness T 1 , the second metal lines have a second thickness T 2 , the third metal lines have a third thickness T 3 , and wherein the second thickness T 2 is less than the first thickness T 1 and the third thickness T 3.
7. The semiconductor structure of claim 6 , wherein the first thickness and the third thickness are substantially equal to each other.
8. The semiconductor structure of claim 1 , wherein
the first metal lines have a first width;
the second metal lines have a second width;
the third metal lines have a third width; and
the second width is less than the first width and the third width.
9. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
the first metal lines have a first pitch P 1 ;
the second metal lines have a second pitch P 2 ;
the third metal lines have a third pitch P 3 ;
the gates have a fourth pitch P 4 , wherein a ratio of the second pitch over the fourth pitch P 2 :P 4 is about 3:2;
the FETs include an n-type conductivity field-effect transistor (nFET) and a p-type conductivity field-effect transistor (pFET) coupled together through a common drain to form an inverter, and
the inverter spans a dimension of about 2*P 4 along the second direction.
10. The semiconductor structure of claim 9 , wherein the second pitch P 2 is less than the first pitch P 1 and the third pitch P 3.
11. The semiconductor structure of claim 9 , wherein
the first metal lines have a first width;
the second metal lines have a second width;
the third metal lines have a third width; and
the second width is less than the first width and the third width.
12. The semiconductor structure of claim 9 , wherein
the first metal lines have a first thickness;
the second metal lines have a second thickness;
the third metal lines have a third thickness; and
the second thickness is less than the first thickness and the third thickness.
13. The semiconductor structure of claim 12 , wherein the first thickness and the third thickness are substantially equal.
14. A semiconductor structure, comprising:
a semiconductor substrate;
a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction;
a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein
the first metal lines have a first pitch P 1 ;
the second metal lines have a second pitch P 2 ;
the third metal lines have a third pitch P 3 ;
the gates have a fourth pitch P 4 , wherein a ratio of the second pitch over the fourth pitch P 2 :P 4 is about 3:2;
the FETs are coupled to a logic gate being one of an NAND gate and an NOR logic gate; and
the logic gate spans a dimension of about 3*P 4 along the second direction.
15. The semiconductor structure of claim 14 , wherein the second pitch P 2 is less than the first pitch P 1 and the third pitch P 3.
16. The semiconductor structure of claim 14 , wherein
the first metal lines have a first thickness;
the second metal lines have a second thickness;
the third metal lines have a third thickness; and
the second thickness is less than the first thickness and the third thickness.
17. The semiconductor structure of claim 16 , wherein the first thickness and the third thickness are substantially equal.
18. The semiconductor structure of claim 14 , wherein
the first metal lines have a first width;
the second metal lines have a second width;
the third metal lines have a third width; and
the second width is less than the first width and the third width.
19. The semiconductor structure of claim 5 , wherein the first pitch P 1 and the third pitch P 3 are substantially equal with a difference (P 3 -P 1 ) less than 15% of P 1.
20. The semiconductor structure of claim 7 , wherein a difference (T 1 -T 3 ) is less than 15% of T 1.