Power module and fabrication method for the same
The power module includes: a ceramics substrate; a source electrode pattern, a drain electrode pattern, a source signal electrode pattern, and a gate signal electrode pattern respectively disposed on the ceramics substrate; a semiconductor device disposed on the drain electrode pattern, the semiconductor device comprising a source pad electrode and a gate pad electrode at a front surface side; a divided leadframe for source bonded to the source electrode pattern and the source pad electrode; and a divided leadframe for gate pad electrode bonded to a gate pad electrode. There is provided a power module having a simplified structure, fabricated through a simplified process, and capable of conducting a large current; and a fabrication method for such a power module.
1. A power module comprising:
a substrate;
a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and
a leadframe bonded to an upper surface of the semiconductor device, wherein
the leadframe is divided into a plurality of leadframes, wherein
the leadframe divided into the plurality of frames comprises:
a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
a second leadframe electrically insulated from the first leadframe, the power module further comprising:
a first bonding wire connecting between the first leadframe and the first signal electrode pattern; and
a second bonding wire connecting between the second leadframe and the second signal electrode pattern.
2. The power module according to claim 1 , wherein
assembling connection between the first leadframe and the second leadframe is performed via an insulating portion.
3. The power module according to claim 2 , wherein
the insulating portion comprises an epoxy based resin or a silicone based resin.
4. The power module according to claim 1 , wherein
the substrate comprises an insulating substrate.
5. The power module according to claim 4 , wherein
the insulating substrate comprises any one selected from the group consisting of a direct bonding copper substrate, a direct brazed aluminum substrate and an active metal bond substrate.
6. The power module according to claim 1 , wherein
the semiconductor device comprises a first pad electrode and a second pad electrode at a front surface side, wherein
the first leadframe is bonded to the first electrode pattern and the first pad electrode, and
the second leadframe is bonded to the second pad electrode.
7. The power module according to claim 1 , wherein
the first leadframe comprises any one selected from the group consisting of Cu, Al, a Cu alloy, an Al alloy, and an alloy containing at least one of the metals, and
the second leadframe comprises any one selected from the group consisting of Cu, Al, and CuMo.
8. The power module according to claim 1 , wherein
the substrate comprises an organic insulating resin layer.
9. The power module according to claim 1 , wherein
the power module comprises any one selected from the group consist of 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, and 7-in-1 module.
10. The power module according to claim 1 , wherein
the semiconductor device comprises any one selected from the group consist of IGBT, a diode, Si based MISFET, SiC based MISFET, and GaNFET.
11. The power module according to claim 1 , wherein
the first electrode pattern and the second electrode pattern are directly disposed on the substrate.
12. A power module comprising:
a substrate;
a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and
a leadframe bonded to an upper surface of the semiconductor device, wherein
the leadframe is divided into a plurality of leadframes, wherein
the leadframe divided into the plurality of frames comprises:
a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
a second leadframe electrically insulated from the first leadframe, the power module further comprising:
a third leadframe electrically connected to the first leadframe, the third leadframe being disposed on the first signal electrode pattern; and
a fourth leadframe electrically connected to the second leadframe, the fourth leadframe being disposed on the second signal electrode pattern.
13. The power module according to claim 12 , wherein
a material of the third leadframe and a material of the first leadframe are the same.
14. The power module according to claim 12 , wherein
a material of the fourth leadframe and a material of the second leadframe are the same.
15. A power module comprising:
a substrate;
a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate;
a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed;
a leadframe bonded to an upper surface of the semiconductor device;
a first soldering layer disposed on the first pad electrode;
a stress relaxation layer disposed on the first soldering layer, the stress relaxation layer configured to relax a stress applied to the first soldering layer; and
a second soldering layer disposed on the stress relaxation layer,
wherein
the leadframe is divided into a plurality of leadframes, wherein
the leadframe divided into the plurality of frames comprises:
a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and
a second leadframe electrically insulated from the first leadframe, wherein
the semiconductor comprises a first pad electrode and a second pad electrode at a front surface side, wherein
the first leadframe is bonded to the first electrode pattern and the first pad electrode,
the second leadframe is bonded to the second pad electrode, and
the first leadframe is connected to the first pad electrode via the stress relaxation layer.
16. The power module according to claim 15 , wherein
the stress relaxation layer is formed by including a metal layer having low coefficient of thermal expansion (CTE).
17. The power module according to claim 16 , wherein
the metal layer having low CTE comprises any one selected from the group consisting of CuMo, CuW, Mo, and W.
18. The power module according to claim 16 , wherein
the stress relaxation layer comprises any one selected from the group consisting of Cu, Al, covar, and invar.