IP Library › Granted Patent US 10,483,255
Granted Patent B2
US 10,483,255 · App. 16/448,241 · Granted Nov 19, 2019

Semiconductor device

Inventors: Hirotaka Takeno (Yokohama, JP); Atsushi Okamoto (Yokohama, JP)
Assignee: SOCIONEXT INC.
H01L27/0207H01L21/823871H01L23/5286H01L27/088H01L27/092H01L27/0924H01L27/11807H01L29/0847H01L29/1095H03K17/161H03K19/0016H01L21/823892H01L27/1203H01L29/0649H01L29/0673H01L29/785H01L2027/11875H01L2027/11881
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Quick Facts
Patent No.
US 10,483,255
App. No.
16/448,241
Granted
Nov 19, 2019
Kind
B2
Abstract

A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

Claims (49)

1. A semiconductor device, comprising:

a substrate;

a first circuit;

a first power supply line;

a second power supply line which is electrically coupled to the first circuit;

a first ground line which is electrically coupled to the first circuit;

a first switch circuit which includes a first switch section;

a first well tap which is electrically coupled to the substrate and the second power supply line;

a second circuit;

a third power supply line;

a fourth power supply line which is electrically coupled to the second circuit;

a second ground line which is electrically coupled to the second circuit; and

a second switch circuit which includes a second switch section,

wherein

the first switch section is adjacent to the first well tap in a plan view,

the first switch section includes a first switch transistor which is disposed between the first power supply line and the second power supply line,

the second switch section is adjacent to no well tap in a plan view,

the second switch section includes a second switch transistor which is disposed between the third power supply line and the fourth power supply line.

2. The semiconductor device as claimed in claim 1 , wherein

the second power supply line, the fourth power supply line, the first ground line, and the second ground line extend in a first direction in a plan view, and

a length of the second switch section in the first direction is shorter than a length of sum of the first switch section and a first well tap in the first direction.

3. The semiconductor device as claimed in claim 2 , wherein

the first switch circuit is located alongside the first circuit in a plan view, and

the second switch circuit is located alongside the second circuit in a plan view.

4. The semiconductor device as claimed in claim 2 , wherein

the semiconductor device includes a plurality of the second switch circuits,

the plurality of the second switch circuits are arranged alongside the second circuit in a plan view, and

the second switch circuits are aligned in a second direction perpendicular to the first direction in a plan view.

5. The semiconductor device as claimed in claim 2 , wherein

the semiconductor device includes a plurality of the second circuits, and

the second switch circuit is located between two of the second circuits in a plan view.

6. The semiconductor device as claimed in claim 2 , wherein

the first circuit, the second circuit, the first switch circuit and the second switch circuit are included in an area,

the fourth power supply line and the second ground line are terminated at an edge of the area which includes the first circuit and the second circuit, and

the second switch circuit is located between the edge of the area and the second circuit.

7. The semiconductor device as claimed in claim 2 , wherein

the second switch circuit include end-cap areas arranged alongside the second switch section on respective sides of the second switch section the first direction.

8. The semiconductor device as claimed in claim 2 , wherein

a second circuit includes a terminal electrically coupled to the first circuit,

the terminal is located at a first side of the second circuit in a plan view, and

the second switch circuit is located alongside a second side of the second circuit which is opposite to the first side in a plan view.

9. The semiconductor device as claimed in claim 2 , wherein

the first power supply line bifurcates in

the first power supply line bifurcates in the first switch circuit in a plan view,

the second power supply line bifurcates in the first switch circuit in a plan view,

the third power supply line bifurcates in the second switch circuit in a plan view, and

the fourth power supply line bifurcates in the second switch circuit in a plan view.

10. The semiconductor device as claimed in claim 1 , wherein

the first switch transistor and the second switch transistor have the same structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2019
From: TAKENO, HIROTAKA; OKAMOTO, ATSUSHI
To: SOCIONEXT INC.
Reel/Frame 049548/0399 →
Priority Claims (1)
JP 2017-089407 · Apr 28, 2017 · national
Continuity (2)
Division 15953899 · Apr 16, 2018
Related Publication 20190312024A1 · Oct 10, 2019