IP Library › Granted Patent US 10,483,264
Granted Patent B2
US 10,483,264 · App. 15/660,970 · Granted Nov 19, 2019

FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions

Inventors: Yen-Wei Tung (Tainan, TW); Jen-Yu Wang (Tainan, TW); Cheng-Tung Huang (Kaohsiung, TW); Yan-Jou Chen (Yunlin County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L27/0924H01L21/0217H01L21/32139H01L21/76224H01L21/823821H01L21/823842H01L21/823878H01L27/0207H01L27/0922H01L29/0649H01L29/66545H01L29/7848H01L29/165H01L29/42364H01L29/42376H01L29/4916H01L29/4966H01L29/517H01L29/518
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Quick Facts
Patent No.
US 10,483,264
App. No.
15/660,970
Granted
Nov 19, 2019
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

Claims (14)

1. A semiconductor device, comprising:

a first MOS region comprises a PMOS region and a second MOS region comprises a NMOS region on a substrate:

a first fin-shaped structure on the PMOS region;

a first single diffusion break (SDB) structure in the first fin-shaped structure;

a first gate structure on the first SDB structure;

a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region of the first MOS region;

a second fin-shaped structure on the NMOS region;

a second SDB structure in the second fin-shaped structure; and

a third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS region of the second MOS region, wherein each of the metal gates on the PMOS region and the NMOS region is transformed from a dummy gate, while the polysilicon gate is an active gate made of polysilicon.

2. The semiconductor device of claim 1 , wherein the first SDB structure comprises silicon nitride.

3. The semiconductor device of claim 1 , wherein the first fin-shaped structure is disposed extending along a first direction and the first SDB structure is disposed extending along a second direction.

4. The semiconductor device of claim 3 , wherein the first direction is orthogonal to the second direction.

5. The semiconductor device of claim 1 , wherein the second fin-shaped structure is disposed extending along a first direction and the second SDB structure is disposed extending along a second direction.

6. The semiconductor device of claim 5 , wherein the first direction is orthogonal to the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: TUNG, YEN-WEI; WANG, JEN-YU; HUANG, CHENG-TUNG; CHEN, YAN-JOU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 043106/0888 →
Priority Claims (1)
TW 106121517 A · Jun 28, 2017 · national
Continuity (1)
Related Publication 20190006360A1 · Jan 3, 2019