High density memory architecture using back side metal layers
A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.
1. A microelectronic memory comprising:
a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
a source line directly contacting the substrate back surface; and
a memory bitcell transistor on the substrate front surface.
2. The microelectronic memory of claim 1 , wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure.
3. The microelectronic memory of claim 2 , wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.
4. The microelectronic memory of claim 1 , further including a word line formed on the substrate back surface.
5. The microelectronic memory of claim 4 , further including a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor.
6. The microelectronic memory of claim 5 , wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.
7. The microelectronic memory of claim 1 , further comprising a memory cell transistor array on the substrate front surface.
8. The microelectronic memory of claim 7 , wherein the memory cell transistor array comprises a plurality of resistance based memory transistors.
9. A microelectronic memory comprising:
a substrate comprising a single material structure, wherein the substrate has a front surface and an opposing back surface,
a word line on the substrate back surface;
a source line positioned between the word line and the substrate; and
a memory bitcell transistor on the substrate front surface.
10. The microelectronic memory of claim 9 , further including a word line strap comprising the word line on the substrate back surface electrically connected to a word line within a memory bitcell transistor.
11. The microelectronic memory of claim 9 , wherein the word line on the substrate back surface is electrically connected to a word line within a memory bitcell transistor through a source/drain structure and a deep diffusion contact within the substrate.
12. The microelectronic memory of claim 9 , further including the source line directly contacting the substrate back surface.
13. The microelectronic memory of claim 12 , wherein the memory bitcell transistor includes at least one source/drain structure formed in the substrate, wherein the source line is electrically connected to the at least one source/drain structure.
14. The microelectronic memory of claim 13 , wherein the source line is electrically connected to the at least one source/drain structure through a deep diffusion contact within the substrate.
15. The microelectronic memory of claim 9 , further comprising a transistor array on the substrate front surface.
16. The microelectronic memory of claim 15 , wherein the transistor array comprises a plurality of resistance based memory transistors.