IP Library Granted Patent US 10,483,406
Granted Patent B2
US 10,483,406 · App. 15/834,590 · Granted Nov 19, 2019

Semiconductor device including an oxide semiconductor

Inventor: Shunpei Yamazaki (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78693G06F3/0412H01L27/14612H01L27/14616H01L29/267H01L29/4908H01L29/512H01L29/518H01L29/78696H01L31/03762H01L31/103G06F3/04886H01L27/323H01L27/3234
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Quick Facts
Patent No.
US 10,483,406
App. No.
15/834,590
Granted
Nov 19, 2019
Kind
B2
Abstract

High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Claims (35)

1. A semiconductor device comprising:

a transistor; and

a photodiode electrically connected to the transistor;

wherein the transistor comprises:

a first oxide semiconductor layer;

a second oxide semiconductor layer over and in direct contact with the first oxide semiconductor layer;

a third oxide semiconductor layer in direct contact with a top surface of the second oxide semiconductor layer;

a gate electrode layer overlapping with the second oxide semiconductor layer with an insulating layer interposed therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the second oxide semiconductor layer,

wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the photodiode is over the transistor.

3. The semiconductor device according to claim 1 , wherein the photodiode is electrically connected to the gate electrode layer of the transistor.

4. The semiconductor device according to claim 1 ,

wherein the insulating layer is over the gate electrode layer, and

wherein the first oxide semiconductor layer is over the insulating layer.

5. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer comprises an impurity imparting an n-type conductivity.

6. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer is in direct contact with a side surface of the second oxide semiconductor layer.

7. A semiconductor device comprising:

a transistor; and

a photodiode electrically connected to the transistor;

wherein the transistor comprises:

a first oxide semiconductor layer;

a second oxide semiconductor layer on and in direct contact with the first oxide semiconductor layer;

a third oxide semiconductor layer in direct contact with a top surface of the second oxide semiconductor layer;

a gate electrode layer overlapping with the second oxide semiconductor layer with an insulating layer interposed therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the second oxide semiconductor layer,

wherein a difference between a Fermi level and a bottom of a conduction band in the second oxide semiconductor layer is smaller than those in the first oxide semiconductor layer and the third oxide semiconductor layer, and

wherein the photodiode comprises an amorphous silicon film.

8. The semiconductor device according to claim 7 , wherein the photodiode is over the transistor.

9. The semiconductor device according to claim 7 , wherein the photodiode is electrically connected to the gate electrode layer of the transistor.

10. The semiconductor device according to claim 7 ,

wherein the insulating layer is over the gate electrode layer, and

wherein the first oxide semiconductor layer is over the insulating layer.

11. The semiconductor device according to claim 7 , wherein the second oxide semiconductor layer comprises an impurity imparting an n-type conductivity.

12. The semiconductor device according to claim 7 , wherein the third oxide semiconductor layer is in direct contact with a side surface of the second oxide semiconductor layer.

Priority Claims (1)
JP 2012-136437 · Jun 15, 2012 · national
Continuity (4)
Continuation 15342333 · Nov 3, 2016
Continuation 14556371 · Dec 1, 2014
Continuation 13914156 · Jun 10, 2013
Related Publication 20180108785A1 · Apr 19, 2018
Cited By (1)
US 12,230,719