Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops

1. A phase selection multiplexer, comprising:

a multiplexer configured to receive a plurality of phases, to select one of the plurality of phases based on a select signal, and to output the selected one of the plurality of phases at an output of the multiplexer;

a flip-flop having a clock input, a data input, and an output, wherein the clock input of the flip-flop is coupled to the output of the multiplexer; and

a gate circuit coupled to the data input of the flip-flop, and also configured to receive the output of the flip-flop and an early output signal generated using another multiplexer, wherein the gate circuit is configured to generate a gate signal based on the output of the flip-flop and the early output signal, and to output the gate signal to the data input of the flip-flop, wherein the gate signal causes the flip-flop to gate the output of the multiplexer during a glitch at the output of the multiplexer.

2. The phase selection multiplexer of claim 1 , wherein the gate circuit is configured to transition the gate signal from logic one to logic zero on a falling edge at the output of the flip-flop, and to transition the gate signal from logic zero to logic one after the glitch.

3. The phase selection multiplexer of claim 2 , wherein the gate circuit is configured to transition the gate signal from logic zero to logic one before a next rising edge at the output of the multiplexer following the glitch.

4. The phase selection multiplexer of claim 1 , further comprising a reset circuit configured to reset the flip-flop on a falling edge at the output of the multiplexer.

5. The phase selection multiplexer of claim 4 , wherein the reset circuit comprises:

an AND gate having a first input, a second input coupled to the output of the flip-flop, and an output coupled to a reset input of the flip-flop; and

an inverter coupled between the output of the multiplexer and the first input of the AND gate.

6. The phase selection multiplexer of claim 1 , wherein the plurality of phases are different phases of a voltage-controlled oscillator, and the output of the flip-flop is coupled to a frequency divider.

7. The phase selection multiplexer of claim 1 , wherein the gate signal is logically low during the glitch at the output of the multiplexer.

8. A phase selection multiplexer comprising:

a first multiplexer configured to receive a plurality of phases, to select a first one of the plurality of phases based on a first select signal, and to output the selected first one of the plurality of phases at an output of the first multiplexer;

a first flip-flop having a clock input, a data input coupled to a first gate signal, and a first output, wherein the clock input of the first flip-flop is coupled to the output of the first multiplexer;

a second multiplexer configured to receive the plurality of phases, to select a second one of the plurality of phases based on a second select signal, and to output the selected second one of the plurality of phases at an output of the second multiplexer;

a second flip-flop having a clock input coupled to the output of the second multiplexer, a data input coupled to a second gate signal, and an output; and

a gate circuit coupled to the output of the first flip-flop and the output of the second flip-flop, wherein the gate circuit is configured to generate the first gate signal, and to output the first gate signal to the data input of the first flip-flop, wherein the gate circuit is configured to generate the first gate signal based on the output of the first flip-flop and the output of the second flip-flop.

9. The phase selection multiplexer of claim 8 , wherein the gate circuit is configured to transition the first gate signal from logic one to logic zero on a falling edge at the output of the first flip-flop, and to transition the first gate signal from logic zero to logic one on a rising edge at the output of the second flip-flop.

10. The phase selection multiplexer of claim 8 , wherein the second gate signal is a logical inverse of the first gate signal.

11. The phase selection multiplexer of claim 8 , wherein the selected second one of the plurality of phases is early relative to the selected first one of the plurality of phases.

12. The phase selection multiplexer of claim 8 , further comprising a select controller configured to generate the first select signal based on a phase select signal, and to phase shift the phase select signal to generate the second select signal.

13. The phase selection multiplexer of claim 12 , wherein, when the phase select signal changes, the selection controller is configured to change the first select signal on a falling edge at the output of the first flip-flop.

14. The phase selection multiplexer of claim 12 , wherein the select controller comprises:

a third flip-flop having a clock input coupled to the second gate signal, a data input coupled to the phase select signal, and an output, wherein the first select signal is output by the output of the third flip-flop;

a phase shifter configured to phase shift the phase select signal to generate a phase-shifted phase select signal; and

a fourth flip-flop having a clock input coupled to the output of the first flip-flop, a data input coupled to the phase-shifted phase select signal, and an output, wherein the second select signal is output by the output of the fourth flip-flop.

15. A method for phase multiplexing, comprising:

receiving a plurality of phases;

selecting one of the plurality of phases based on a select signal using a multiplexer;

outputting the selected one of the plurality of phases at an output of the multiplexer to a flip-flop; and

gating the output of the multiplexer using the flip-flop and a gating circuit configured to receive the output of the flip-flop and an early output signal generated using another multiplexer and generate a gating signal based on the output of the flip-flop and the early output signal, the gating signal causing the flip-flop to gate the output of the multiplexer during a glitch at the output of the multiplexer.

16. The method of claim 15 , wherein gating the output of the multiplexer comprises:

starting the gating on a falling edge at the output of the multiplexer; and

ceasing the gating after the glitch.

17. The method of claim 15 , wherein the output of the multiplexer is coupled to a clock input of the flip-flop, and gating the output of the multiplexer during the glitch comprises:

generating a gate signal with the gating circuit; and

inputting the gate signal to a data input of the flip-flop, wherein the gate signal causes the flip-flop to gate the output of the multiplexer during the glitch.

18. The method of claim 16 , further comprising changing the select signal on the falling edge at the output of the multiplexer, wherein the change in the select signal causes the glitch at the output of the multiplexer.

19. The method of claim 16 , wherein the gating ceases before a next rising edge at the output of the multiplexer following the glitch.

20. A method for phase multiplexing comprising:

receiving a plurality of phases;

selecting one of the plurality of phases based on a first select signal using a first multiplexer;

outputting the selected one of the plurality of phases at an output of the first multiplexer to a first flip-flop;

selecting a second one of the plurality of phases based on a second select signal using a second multiplexer;

outputting the selected second one of the plurality of phases at an output of the second multiplexer to a second flip-flop; and

gating the output of the first multiplexer using the first flip-flop and a gating circuit causing the first flip-flop to gate the output of the first multiplexer during a glitch at the output of the first multiplexer using a gating signal based on an output of the first flip-flop and an output of the second flip-flop.

21. The method of claim 20 , wherein the selected second one of the plurality of phases is early relative to the selected first one of the plurality of phases.

22. The method of claim 20 , further comprising:

generating the first select signal based on a phase select signal; and

phase shifting the phase select signal to generate the second select signal.

23. An apparatus for phase multiplexing, comprising:

means for receiving a plurality of phases;

means for selecting one of the plurality of phases based on a select signal;

means for outputting the selected one of the plurality of phases at an output; and

means for gating the output during a glitch at the output, the means for gating including a flip-flop and a gating circuit causing the flip-flop to gate the output, wherein the gating circuit is configured to receive the output of the flip-flop and an early output signal generated using another multiplexer and to generate a gating signal based on the output of the flip-flop and the early output signal.

24. The apparatus of claim 23 , wherein the means for gating the output comprises:

means for starting the gating on a falling edge at the output; and

means for ceasing the gating after the glitch.

25. The apparatus of claim 24 , wherein the gating ceases before a next rising edge at the output following the glitch.

26. The method of claim 20 , wherein gating the output of the first multiplexer with the first flip-flop comprises:

starting the gating on a falling edge at the output of the first multiplexer; and

ceasing the gating on a rising edge at the output of the second multiplexer.

27. An apparatus for phase multiplexing comprising:

means for receiving a plurality of phases;

means for selecting a first one of the plurality of phases based on a first select signal;

means for outputting the selected first one of the plurality of phases at a first output, the means for outputting the first one of the plurality of phases including a first flip-flop;

means for selecting a second one of the plurality of phases based on a second select signal;

means for outputting the selected second one of the plurality of phases at a second output, the means for outputting the second one of the plurality of phases including a second flip-flop; and

means for gating the first output during a glitch, the means for gating including a gating circuit receiving the first output and the second output and causing the first flip-flop to gate the means for selecting the first one of the plurality of phases based on the first output and the second output.

28. The apparatus of claim 27 , wherein the selected second one of the plurality of phases is early relative to the selected first one of the plurality of phases.

29. The apparatus of claim 28 , further comprising:

means for generating the first select signal based on a phase select signal; and

means for phase shifting the phase select signal to generate the second select signal.

30. The apparatus of claim 27 , wherein the means for gating the first output comprises:

means for starting the gating on a falling edge at the first output; and

means for ceasing the gating on a rising edge at the second output.