IP Library Granted Patent US 10,485,293
Granted Patent B2
US 10,485,293 · App. 15/634,693 · Granted Nov 26, 2019

Semiconductor device and electronic apparatus with metal-containing film layer at bonding surface thereof

Inventors: Yoshiya Hagimoto (Kanagawa, JP); Nobutoshi Fujii (Kanagawa, JP); Kenichi Aoyagi (Kanagawa, JP)
Assignee: Sony Corporation
A43B13/14A43B7/24A43B13/12A43B13/125A43B13/141A43B13/183A43B13/185
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Quick Facts
Patent No.
US 10,485,293
App. No.
15/634,693
Granted
Nov 26, 2019
Kind
B2
Abstract

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

Claims (48)

1. A semiconductor device, comprising:

a semiconductor substrate;

an interlayer insulating layer formed on the semiconductor substrate;

a bonding electrode formed in the interlayer insulating layer such that the bonding electrode and the interlayer insulating layer form a planar surface including a first region corresponding to the bonding electrode and a second region corresponding to the interlayer insulating layer; and

a metal film layer which covers the planar surface,

wherein the metal film layer includes a material and is exposed to a heat treatment, and the heat treatment causes at least a part of the material that contacts the interlayer insulating layer to react with the interlayer insulating layer.

2. The semiconductor device according to claim 1 ,

wherein the material is a metal which becomes an insulator due to a reaction with the interlayer insulating layer.

3. The semiconductor device according to claim 1 ,

wherein the material includes at least one type selected from Ta or Ti.

4. A semiconductor device including a first semiconductor substrate and a second semiconductor substrate which are formed by laminating surfaces of bonding electrodes through metal films, the semiconductor device comprising:

the first semiconductor substrate;

a first interlayer insulating layer formed on the first semiconductor substrate;

a first bonding electrode formed in the first interlayer insulating layer such that the first bonding electrode and the first interlayer insulating layer form a first planar surface including a first region corresponding to the first bonding electrode and a second region corresponding to the first interlayer insulating layer;

the second semiconductor substrate bonded to the first semiconductor substrate;

a second interlayer insulating layer formed on the second semiconductor substrate;

a second bonding electrode formed in the second interlayer insulating layer such that the second bonding electrode and the second interlayer insulating layer form a second planar surface including a third region corresponding to the second bonding electrode and a fourth region corresponding to the second interlayer insulating layer;

a first metal film layer formed between the first planar surface and the second planar surface,

wherein the first metal film layer includes a first material that reacts with the first interlayer insulating layer in a case where the first material contacts the first interlayer insulating layer and is exposed to a heat treatment.

5. An electronic apparatus, comprising:

a semiconductor device which includes

a semiconductor substrate,

an interlayer insulating layer formed on the semiconductor substrate,

a bonding electrode formed in the interlayer insulating layer such that the bonding electrode and the interlayer insulating layer form a planar surface including a first region corresponding to the bonding electrode and a second region corresponding to the interlayer insulating layer, and

a metal film layer which covers the planar surface; and

a signal processing circuit configured to process an output signal of the semiconductor device,

wherein the metal film layer includes a material that reacts with the interlayer insulating layer in a case where the material contacts the interlayer insulating layer and is exposed to a heat treatment.

6. The semiconductor device according to claim 1 , further comprising a barrier surface layer between the interlayer insulating layer and the bonding electrode.

7. The semiconductor device according to claim 6 , wherein the barrier surface layer includes a material selected from the group consisting of Ta, Ti, Ru, TaN, and TiN.

8. The semiconductor device according to claim 1 , wherein the interlayer insulating layer includes an oxide, or a nitride layer and a metallic oxide.

9. The semiconductor device according to claim 1 , wherein the bonding electrode includes Cu.

10. The semiconductor device according to claim 1 , wherein a thickness of the metal film layer is equal to or less than 100 nm.

11. The semiconductor device according to claim 7 , wherein a thickness of the metal film layer is equal to or less than 20 nm.

12. The semiconductor device according to claim 4 , further comprising a barrier surface layer between the first interlayer insulating layer and the first bonding electrode.

13. The semiconductor device according to claim 4 , further comprising:

a second metal film layer formed between the first planar surface and the second planar surface,

wherein the second metal film layer includes a second material that reacts with the second interlayer insulating layer in a case where the second material contacts the second interlayer insulating layer and is exposed to the heat treatment.

14. The semiconductor device according to claim 13 , further comprising:

a first barrier surface layer between the first interlayer insulating layer and the first bonding electrode; and

a second barrier surface layer between the second interlayer insulating layer and the second bonding electrode.

15. The semiconductor device according to claim 4 , wherein the first interlayer insulating layer and/or the second interlayer insulating layer includes an oxide, or a nitride layer and a metallic oxide.

16. The semiconductor device according to claim 4 , wherein the first bonding electrode and/or the second bonding electrode includes Cu.

17. The semiconductor device according to claim 4 , wherein a thickness of the first metal film layer is equal to or less than 100 nm.

18. The semiconductor device according to claim 17 , wherein a thickness of the first metal film layer is equal to or less than 20 nm.

19. The semiconductor device according to claim 4 , wherein a thickness of a reaction product of the first metal film layer and the first interlayer insulating layer is equal to or more than 5 molecular layers.

20. An electronic apparatus comprising:

the semiconductor device according to claim 4 ; and

a signal processing circuit configured to process an output signal of the semiconductor device.

Priority Claims (1)
JP 2012-029429 · Feb 14, 2012 · national
Continuity (3)
Continuation 14827883 · Aug 17, 2015
Division 13755881 · Jan 31, 2013
Related Publication 20170354199A1 · Dec 14, 2017
Cited By (1)
US 12,708,016