IP Library Granted Patent US 10,488,587
Granted Patent B2
US 10,488,587 · App. 15/699,707 · Granted Nov 26, 2019

Methods of fabricating integrated circuit devices with components on both sides of a semiconductor layer

Inventors: Alain Chantre (Seyssins, FR); Sébastien Cremer (Sassenage, FR)
Assignees: STMicroelectronics SA; STMicroelectronics (Crolles 2) SAS
G02B6/12002G02B6/12004H01S5/026H01S5/1032H01S5/021H01S5/0262H01S5/0422H01S5/34306H01S2301/176
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Quick Facts
Patent No.
US 10,488,587
App. No.
15/699,707
Granted
Nov 26, 2019
Kind
B2
Abstract

A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.

Claims (64)

1. A method of making an integrated circuit, the method comprising:

providing a first substrate comprising a carrier substrate, a buried insulating layer, and a semiconductor layer above the buried insulating layer, the buried insulating layer being above the carrier substrate, the first substrate having a first side and an opposite second side, the semiconductor layer having a first semiconductor layer side and a second semiconductor layer side;

from the first semiconductor layer side, forming a first waveguide in the semiconductor layer;

forming a first insulating layer over the first side of the first substrate;

forming a metallization level comprising a metal line within the first insulating layer;

attaching a second substrate over the first insulating layer;

flipping the first substrate after the attaching;

from the second side of the first substrate, removing the carrier substrate and the buried insulating layer after the flipping the first substrate after the attaching;

forming a laser source over the second semiconductor layer side of the semiconductor layer, the laser source being formed directly over the first waveguide; and

encapsulating the laser source in a second insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

2. The method of claim 1 , wherein forming the laser source comprises:

depositing a n-type semiconductor layer stack over the second semiconductor layer side of the semiconductor layer;

depositing a quantum well layer stack over the n-type semiconductor layer stack;

depositing a p-type semiconductor layer stack over the quantum well layer stack; and

patterning the p-type semiconductor layer stack, the quantum well layer stack, and the n-type semiconductor layer stack.

3. The method of claim 2 , wherein forming the laser source comprises:

forming a first eutectic deposit on the patterned p-type semiconductor layer stack; and

forming a second eutectic deposit on the patterned n-type semiconductor layer stack.

4. The method of claim 3 , further comprising: forming contacts to the first eutectic deposit and the second eutectic deposit, the contacts being formed in the second insulating layer.

5. The method of claim 2 , wherein the n-type semiconductor layer stack comprises n-type InP/InGaAs stack, the quantum well layer stack comprises InGaAsP, and the p-type semiconductor layer stack comprises p-type InP.

6. The method of claim 1 , further comprising:

depositing a third insulating layer before forming the second insulating layer, the third insulating layer contacting the exposed major surface of the semiconductor layer;

depositing an amorphous silicon layer over the third insulating layer; and

patterning the amorphous silicon layer to form a second waveguide directly above the first waveguide.

7. The method of claim 1 , further comprising:

forming a grating coupler in the semiconductor layer, the grating coupler being proximate to the first waveguide.

8. The method of claim 7 , further comprising forming a mirror in the first insulating layer, the mirror being directly formed over the grating coupler.

9. The method according to claim 8 , aligning the grating coupler with the mirror so that light via the semiconductor layer is divided in the grating coupler into a first beam that crosses the second insulating layer toward an optical fiber interface at an exposed surface of the second insulating layer and into a second beam toward the mirror and reflected toward the optical fiber interface.

10. The method according to claim 7 , further comprising forming a modulator in the semiconductor layer, the modulator being proximate the grating coupler.

11. The method of claim 1 , wherein forming the metallization level further comprises forming a heat dissipating radiator in the first insulating layer, wherein the heat dissipating radiator is formed directly over the first waveguide.

12. A method of making an integrated circuit, the method comprising:

providing a first substrate comprising a carrier substrate, a buried insulating layer, and a semiconductor layer, the first substrate having a first side and an opposite second side, the semiconductor layer having a first semiconductor layer side and a second semiconductor layer side;

forming a first waveguide in the semiconductor layer;

forming a metallization level comprising a metal line over the first side of the first substrate;

attaching a second substrate over the metallization level;

flipping the first substrate after the attaching;

from the second side of the first substrate, removing the carrier substrate and the buried insulating layer after the flipping the first substrate after the attaching;

fabricating a laser source over and in contact with the second semiconductor layer side of the semiconductor layer, the laser source being fabricated to be aligned with the first waveguide; and

encapsulating the laser source in a second insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

13. A method of making an integrated circuit, the method comprising:

providing a first substrate comprising a carrier substrate, a buried insulating layer, and a semiconductor layer, the first substrate having a first side and an opposite second side, the semiconductor layer having a first semiconductor layer side and a second semiconductor layer side;

forming a first waveguide in the semiconductor layer;

forming a metallization level comprising a metal line over the first side of the first substrate;

attaching a second substrate over the metallization level;

flipping the first substrate after the attaching;

from the second side of the first substrate, removing the carrier substrate and the buried insulating layer after the flipping the first substrate after the attaching;

depositing a n-type semiconductor layer stack over and in contact with the second semiconductor layer side of the semiconductor layer;

depositing a quantum well layer stack over the n-type semiconductor layer stack;

depositing a p-type semiconductor layer stack over the quantum well layer stack; and

forming a laser source by patterning the p-type semiconductor layer stack, the quantum well layer stack, and the n-type semiconductor layer stack, the laser source being patterned to be aligned with the first waveguide; and

encapsulating the laser source in a second insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

14. A method of making an integrated circuit, the method comprising:

providing a first substrate comprising a carrier substrate, a buried insulating layer, and a semiconductor layer, the first substrate having a first side and an opposite second side, the semiconductor layer having a first semiconductor layer side and a second semiconductor layer side;

forming a first waveguide in the semiconductor layer;

forming a metallization level comprising a metal line over the first side of the first substrate;

attaching a second substrate over the metallization level;

flipping the first substrate after the attaching;

from the second side of the first substrate, removing the carrier substrate and the buried insulating layer after the flipping the first substrate after the attaching;

fabricating a laser source over and in contact with the second semiconductor layer side of the semiconductor layer by depositing and patterning a heterostructure comprising a n-type InP/InGaAs layer, a InGaAsP quantum well layer, and a p-type InP layer, the patterning being aligned with the first waveguide; and

encapsulating the laser source in a second insulating layer, wherein the integrated circuit comprising the first waveguide and the laser source forms part of a photonic integrated circuit.

15. The method of claim 14 , wherein fabricating the laser source comprises:

forming a first eutectic deposit on the patterned p-type InP layer; and

forming a second eutectic deposit on the patterned n-type InP/InGaAs layer.

16. The method of claim 15 , further comprising: forming contacts to the first eutectic deposit and the second eutectic deposit, the contacts being formed in the second insulating layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2022
From: STMICROELECTRONICS (CROLLES 2) SAS
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060784/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2022
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060620/0769 →
Priority Claims (1)
FR 13 55991 · Jun 24, 2013 · national
Continuity (2)
Continuation 14311496 · Jun 23, 2014
Related Publication 20170371099A1 · Dec 28, 2017
Cited By (2)
US 12,189,262 US 12,374,858