IP Library Granted Patent US 10,489,332
Granted Patent B2
US 10,489,332 · App. 14/015,561 · Granted Nov 26, 2019

System and method for per-task memory protection for a non-programmable bus master

Inventors: Balatripura Sodemma Chavali (Sugar Land, TX); Karl Friedrich Greb (Sugar Land, TX); Rajeev Suvarna (Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
G06F13/4068G06F12/1416G06F12/1458G06F12/1483G06F13/1605G06F13/4221G06F2212/1016G06F2212/1052
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Quick Facts
Patent No.
US 10,489,332
App. No.
14/015,561
Granted
Nov 26, 2019
Kind
B2
Abstract

A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Claims (18)

1. A system, comprising:

a non-programmable bus master, comprising:

a memory protection unit (MPU) configured to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, wherein:

the MPU operating in the first configuration with the first set of access permissions is configured to permit a transaction to access a bus slave; and

the MPU operating in the second configuration with the second set of access permissions is configured to:

deny a transaction access to the bus slave; and

communicate a response in response to denying the transaction access to the bus slave; and

a direct memory access (DMA) controller configured to:

execute a first task and a second task, wherein the first and second tasks are configured to generate transactions;

cause the MPU to operate in the first configuration when the DMA controller executes the first task; and

cause the MPU to operate in the second configuration when the DMA controller executes the second task.

2. The system of claim 1 wherein the DMA controller sends a task identification (ID) to the MPU and, upon receipt of a task ID, the MPU operates in one of the configurations based on the task ID.

3. The system of claim 1 wherein the DMA controller automatically changes the configuration of the MPU without sending a task identification (ID) to the MPU.

4. The system of claim 1 wherein the MPU is configured to permit or deny a transaction access to the bus slave based on one selected from the group consisting of:

an address to which the transaction is directed;

a privilege level associated with the task that generated the transaction;

a security level associated with the task that generated the transaction; and

whether the transaction was generated by a functional unit of the bus master or a debug unit of the bus master.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2013
From: CHAVALI, BALATRIPURA SODEMMA; GREB, KARL FRIEDRICH; SUVARNA, RAJEEV
To: TEXAS INSTRUMENTS INCORPORATED
Reel/Frame 031336/0449 →
Continuity (2)
Provisional Application 61762212 · Feb 7, 2013
Related Publication 20140223047A1 · Aug 7, 2014