IP Library › Granted Patent US 10,489,339

Granted Patent B2

US 10,489,339 · App. 16/040,977 · Granted Nov 26, 2019

Sensor bus communication system

Inventor: Amit Kumar Srivastava (Folsom, CA)

Assignee: Intel Corporation

G06F13/4291 G06F1/324 G06F13/1673 G06F13/364

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Quick Facts

Patent No.: US 10,489,339
App. No.: 16/040,977
Granted: Nov 26, 2019
Kind: B2

External Links

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Abstract

Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

Claims (72)

1. An apparatus comprising:

a first circuitry comprising a first input/output (IO) interface;

a second circuitry comprising a second IO interface;

a third circuitry to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface; and

a Bus Characteristics Register (BCR) to store at least 8 bits,

wherein the first IO interface comprises an Improved Inter Integrated Circuit (I3C) interface which is operable at a first frequency;

wherein the second IO interface is operable at a second frequency less than the first frequency, the second IO interface comprising: an Inter Integrated Circuit (I2C) interface, a Serial Peripheral Interface (SPI) interface, or a UART (Universal Asynchronous Receiver/Transmitter); and

wherein the BCR includes a device role field having at least a first value indicating that the apparatus comprises an I3C slave, and a second value indicating that the apparatus comprises an I3C master.

2. The apparatus of claim 1 ,

wherein the BCR includes a bridge identifier field having at least a first value indicating that the apparatus comprises an I3C bridge device, and a second value indicating that the apparatus does not comprise an I3C bridge device.

3. The apparatus of claim 1 ,

wherein the BCR includes an offline capable field having at least a first value indicating that the apparatus will always respond to I3C bus commands, and a second value indicating that the apparatus will not always respond to I3C bus commands.

4. The apparatus of claim 1 , comprising:

a Legacy Register (LVR) that includes an I2C mode indicator field having at least a first value indicating that the I2C interface supports Fast-mode (Fm), and a second value indicating that the I2C interface supports Fast-mode plus (Fm+).

5. The apparatus of claim 1 ,

wherein the first IO interface is to process a Set Bridge Targets (SETBRGTGT) I3C command code carrying information regarding one or more endpoints the apparatus is communicating with, the information comprising at least: a dynamic address indicator, or a type/ID indicator.

6. The apparatus of claim 1 ,

wherein the third circuitry is to write the transaction received on the second IO interface into a first buffer at the second frequency, and is to retrieve the transaction received on the second IO interface from the first buffer at the first frequency; and

wherein the third circuitry is to write the transaction received on the first IO interface into a second buffer at the first frequency, and is to retrieve the transaction received on the first IO interface from the second buffer at the second frequency.

7. An apparatus comprising:

a first transceiver coupled to a first input/output (IO) interface comprising a serial data bus;

a second transceiver coupled to a second IO interface comprising a serial data bus;

a third transceiver coupled to a third IO interface; and

a Bus Characteristics Register (BCR) to store at least 8 bits,

wherein the serial data bus of the first IO interface is an Improved Inter Integrated Circuit (I3C) interface which is operable at a first frequency;

wherein the serial data bus of the second IO interface is an Inter Integrated Circuit (I2C) interface which is operable at a second frequency less than the first frequency;

wherein the third IO interface comprises: a Serial Peripheral Interface (SPI) interface, or a Universal Asynchronous Receiver/Transmitter (UART); and

8. The apparatus of claim 7 ,

9. The apparatus of claim 7 ,

10. The apparatus of claim 7 , comprising:

11. The apparatus of claim 7 ,

12. The apparatus of claim 7 , comprising:

a circuitry to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface,

13. A system comprising a memory, a processor coupled to the memory, and a wireless interface to allow the processor to communicate with another device, the processor and an apparatus including:

a first circuitry comprising a first input/output (IO) interface;

a second circuitry comprising a second IO interface;

a Bus Characteristics Register (BCR) to store at least 8 bits,

wherein the first IO interface comprises an Improved Inter Integrated Circuit (I3C) interface which is operable at a first frequency;

14. The system of claim 13 ,

15. The system of claim 13 ,

16. The system of claim 13 , comprising:

17. The system of claim 13 ,

18. A method comprising:

receiving a transaction on a first input/output (IO) interface;

receiving a transaction on a second IO interface;

converting the transaction received on the first IO interface into a transaction for the second IO interface; and

converting the transaction received on the second IO interface into a transaction for the first IO interface,

wherein the first IO interface comprises an Improved Inter Integrated Circuit (I3C) interface which is operable at a first frequency, and which comprises a Bus Characteristics Register (BCR) to store at least 8 bits;

19. The method of claim 18 ,

20. The method of claim 18 ,

21. The method of claim 18 ,

22. The method of claim 18 , comprising:

Continuity (2)

Continuation 15086700 · Mar 31, 2016

Related Publication 20190138490A1 · May 9, 2019

Cited By (1)

US 12,517,997