IP Library Granted Patent US 10,490,410
Granted Patent B2
US 10,490,410 · App. 16/235,081 · Granted Nov 26, 2019

Self-protective layer formed on high-K dielectric layer

Inventors: Ju-Li Huang (Mingjian Township, TW); Ying-Liang Chuang (Zhubei, TW); Ming-Hsi Yeh (Hsinchu, TW); Kuo-Bin Huang (Jhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L21/28247H01L21/28088H01L21/28185H01L21/32134H01L21/823821H01L21/823842H01L21/823857H01L27/0924H01L29/4966H01L29/517H01L29/66545H01L29/66568H01L29/66795H01L21/28079
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Quick Facts
Patent No.
US 10,490,410
App. No.
16/235,081
Granted
Nov 26, 2019
Kind
B2
Abstract

Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.

Claims (33)

1. A method for forming a semiconductor device, comprising:

patterning a first work function metal on a gate dielectric layer disposed on a substrate using an etching solution, wherein the etching solution includes phosphoric acid and hydrogen peroxide in an acid solution; and

upon removal of the first work function metal from the substrate, forming a self-protective layer comprising a metal phosphate on the gate dielectric layer by exposing the gate dielectric layer to the etching solution.

2. The method of claim 1 , further comprising:

forming a second work function metal on the self-protective layer.

3. The method of claim 2 , wherein the self-protective layer comprises the metal phosphate having a common metal element with the gate dielectric layer.

4. The method of claim 3 , wherein the common metal element is at least one of Ta, Ti, Hf, Zr, or a combination thereof.

5. The method of claim 1 , further comprising:

forming a metal barrier on the self-protective layer, wherein the metal barrier bonds with a metal phosphate from the self-protective layer.

6. The method of claim 1 , wherein the gate dielectric layer is hafnium oxide.

7. A method of manufacturing a semiconductor device, the method comprising:

depositing a gate dielectric between spacers over a semiconductor fin;

depositing a first work function layer over the gate dielectric;

applying an etchant to the first work function layer, wherein the etchant will both remove a portion of the first work function layer and also react with a portion of the gate dielectric to form a self-protective layer, the self protective layer comprising a metal phosphate.

8. The method of claim 7 , further comprising forming a second work function layer in physical contact with the self-protective layer.

9. The method of claim 7 , wherein a metal within the metal phosphate comes from the gate dielectric.

10. The method of claim 9 , wherein the metal is at least one of Ta, Ti, Hf, or Zr.

11. The method of claim 7 , further comprising forming a metal barrier on the self-protective layer, wherein the metal barrier bonds with a metal phosphate from the self-protective layer.

12. The method of claim 7 , wherein the gate dielectric is zirconium oxide.

13. The method of claim 7 , wherein the etchant comprises phosphoric acid.

14. The method of claim 13 , wherein the etchant further comprises hydrogen peroxide.

15. A method of manufacturing a semiconductor device, the method comprising:

removing a dummy gate from over a semiconductor fin;

depositing a high-k gate dielectric layer over the semiconductor fin, the high-k gate dielectric layer comprising a first reactant after the depositing the high-k gate dielectric layer;

depositing a first work function layer over the high-k gate dielectric layer;

using an etchant to remove a portion of the first work function layer and expose the high-k gate dielectric layer, the etchant comprising a second reactant;

reacting the first reactant and the second reactant to form a self-protective layer, the self-protective layer being located over a portion of the high-k gate dielectric layer and comprising a metal phosphate; and

depositing a gate electrode over the self-protective layer.

16. The method of claim 15 , wherein the depositing the gate electrode comprises depositing a second work function layer.

17. The method of claim 15 , wherein the first reactant is a metal reactant.

18. The method of claim 17 , wherein the metal reactant is hafnium.

19. The method of claim 17 , wherein the metal reactant is tantalum.

20. The method of claim 15 , further comprising forming a metal barrier on the self-protective layer, wherein the metal barrier bonds with the metal phosphate from the self-protective layer.

Continuity (2)
Division 15718565 · Sep 28, 2017
Related Publication 20190164766A1 · May 30, 2019