IP Library › Granted Patent US 10,490,531
Granted Patent B2
US 10,490,531 · App. 15/912,597 · Granted Nov 26, 2019

Manufacturing method of semiconductor device and semiconductor device

Inventors: Tetsuya Kurosawa (Yokkaichi, JP); Takanobu Ono (Kuwana, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L25/0657H01L23/13H01L24/29H01L24/48H01L24/73H01L24/83H01L25/0652H01L25/50H01L23/3128H01L2224/45144H01L2224/73265H01L2224/92247H01L2225/0651H01L2225/06506H01L2225/06562H01L2924/15311
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Quick Facts
Patent No.
US 10,490,531
App. No.
15/912,597
Granted
Nov 26, 2019
Kind
B2
Abstract

A manufacturing method of a semiconductor device according to the present embodiment includes forming a modified layer with distortion in semiconductor crystals in a first and a second semiconductor wafers by radiating laser to a dicing region of the first and second semiconductor wafers, each of the first and second semiconductor wafers including a plurality of semiconductor chips. The method also includes stacking the second semiconductor wafer on the first semiconductor wafer to be shifted in a first direction. The first direction is a direction from a first side of a first semiconductor chip of the first semiconductor wafer towards an opposite side to the first side of the first semiconductor chip. The method further includes cleaving the first and second semiconductor wafers.

Claims (37)

1. A manufacturing method of a semiconductor device, the method comprising:

forming a modified layer with distortion in semiconductor crystals in a first and a second semiconductor wafers by radiating laser to a dicing region of the first and second semiconductor wafers, each of the first and second semiconductor wafers including a plurality of semiconductor chips;

stacking the second semiconductor wafer on the first semiconductor wafer to be shifted in a first direction, the first direction being a direction from a first side of a first semiconductor chip of the first semiconductor wafer towards an opposite side to the first side of the first semiconductor chip; and

cleaving the first and second semiconductor wafers after stacking the second semiconductor wafer on the first semiconductor wafer.

2. The method of claim 1 , further comprising

forming a first adhesive on front surfaces of the first semiconductor chip included in the first semiconductor wafer to cover a region from the opposite side to the first side of the first semiconductor chip to a first boundary in front of bonding pads provided on the first semiconductor chip and not to cover a region from the first boundary to the first side of the first semiconductor chip, wherein

the second semiconductor wafer is stacked on the first semiconductor wafer such that a side of a second semiconductor chip of the second semiconductor wafer is shifted from the first side of the first semiconductor chip of the first semiconductor wafer to the first boundary of the first semiconductor chip.

3. The method of claim 1 , further comprising:

stacking third to n-th semiconductor wafers (n is an integer equal to or more than 3) having substantially same configurations as the first and second semiconductor wafers on the second semiconductor wafer; and

cleaving the stacked first to n-th semiconductor wafers, wherein

the second to n-th semiconductor wafers are stacked to be shifted in the first direction with respect to corresponding semiconductor wafers directly below, respectively.

4. The method of claim 2 , further comprising:

stacking third to n-th semiconductor wafers (n is an integer equal to or more than 3) having substantially same configurations as the first and second semiconductor wafers on the second semiconductor wafer; and

cleaving the stacked first to n-th semiconductor wafers, wherein

the second to n-th semiconductor wafers are stacked to be shifted in the first direction with respect to corresponding semiconductor wafers directly below, respectively.

5. The method of claim 2 , wherein

the first adhesive is a photosensitive adhesive, and

in the forming the first adhesive, the first adhesive is provided on the first semiconductor wafer and is thereafter processed by a lithography technology to cover the region from the opposite side to the first side of the first semiconductor chip to the first boundary in front of the bonding pads provided on the first semiconductor chip and not to cover the region from the first boundary to the first side of the first semiconductor chip.

6. The method of claim 3 , wherein

the first adhesive is a photosensitive adhesive, and

in the forming the first adhesive, the first adhesive is provided on the first semiconductor wafer and is thereafter processed by a lithography technology to cover the region from the opposite side to the first side of the first semiconductor chip to the first boundary in front of the bonding pads provided on the first semiconductor chip and not to cover the region from the first boundary to the first side of the first semiconductor chip.

7. The method of claim 1 , wherein the stacking includes:

pressing the first and second semiconductor wafers by a first pressure; and

pressing the first and second semiconductor wafers by a second pressure higher than the first pressure, after pressing by the first pressure.

8. The method of claim 2 , wherein the stacking includes:

pressing the first and second semiconductor wafers by a first pressure; and

pressing the first and second semiconductor wafers by a second pressure higher than the first pressure, after pressing by the first pressure.

9. The method of claim 3 , wherein

the stacking includes:

pressing the first and second semiconductor wafers by a first pressure; and

pressing the first and second semiconductor wafers by a second pressure higher than the first pressure, after pressing by the first pressure.

10. The method of claim 1 , wherein the semiconductor chips of the first and second semiconductor wafers respectively have substantially same configurations.

11. The method of claim 1 , further comprising:

after cleaving the first and second semiconductor wafers,

mounting stacked semiconductor chips on a mounting board;

bonding a plurality of bonding pads provided on the semiconductor chips to the mounting board with wires; and

covering the semiconductor chips and the wires with a resin.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2018
From: KUROSAWA, TETSUYA; ONO, TAKANOBU
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045112/0172 →
Priority Claims (1)
JP 2017-180375 · Sep 20, 2017 · national
Continuity (1)
Related Publication 20190088624A1 · Mar 21, 2019