IP Library › Granted Patent US 10,490,556
Granted Patent B1
US 10,490,556 · App. 16/048,335 · Granted Nov 26, 2019

Semiconductor device and method for fabricating the same

Inventors: Yu-Shan Su (Taipei, TW); Chia-Wei Wu (Taichung, TW); Ting-Pang Chung (Taichung, TW)
Assignees: UNITED MICROELECTRONICS CORP.; Fujian Jinhua Integrated Circuit Co., Ltd.
H01L27/10894H01L21/0217H01L21/0228H01L21/0234H01L21/02164H01L21/31055H01L21/76229H01L27/10897H01L29/0649
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Quick Facts
Patent No.
US 10,490,556
App. No.
16/048,335
Granted
Nov 26, 2019
Kind
B1
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.

Claims (26)

1. A semiconductor device, comprising:

a substrate having a memory region and a periphery region;

a first isolation structure in the substrate on the memory region, wherein the first isolation comprises:

a first liner in the substrate;

a second liner on the first liner; and

a third liner on the second liner, wherein a top surface of the third liner is planar;

a second isolation structure adjacent to the first isolation structure, wherein a width of the second isolation structure is greater than a width of the first isolation structure, the second isolation structure comprises:

the first liner in the substrate;

the second liner on the first liner;

the third liner on the second liner, wherein a top surface of the third liner comprises a V-shape;

a fourth liner on the third liner, wherein the fourth liner comprises a V-shape; and

a fifth liner on the fourth liner, wherein a top surface of the fifth liner is planar.

2. The semiconductor device of claim 1 , further comprising a third isolation structure in the substrate on the periphery region, wherein a width of the third isolation structure is greater than a width of the second isolation structure.

3. The semiconductor device of claim 2 , wherein the third isolation structure comprises:

the first liner in the substrate;

the second liner on the second liner; and

the third liner on the second liner.

4. The semiconductor device of claim 3 , further comprising:

the fourth liner on the third liner in the second isolation structure and the third isolation structure;

the fifth liner on the fourth liner in the second isolation structure and the third isolation structure; and

a sixth liner on the fifth liner in the third isolation structure.

5. The semiconductor device of claim 4 , wherein the third liner and the fourth liner comprise different materials.

6. The semiconductor device of claim 4 , wherein the third liner comprises silicon nitride and the fourth liner comprises silicon oxide.

7. The semiconductor device of claim 4 wherein the third liner and the fifth liner comprise a same material.

8. The semiconductor device of claim 7 , wherein the third liner and the fifth liner comprise silicon nitride.

9. The semiconductor device of claim 1 , wherein the first liner and the second liner comprise silicon oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2018
From: SU, YU-SHAN; WU, CHIA-WEI; CHUNG, TING-PANG
To: UNITED MICROELECTRONICS CORP.; FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.
Reel/Frame 046494/0157 →
Priority Claims (1)
CN 2018 1 0706674 · Jul 2, 2018 · national
Cited By (1)
US 12,342,536