Semiconductor memory device having buried word line with a neck profile portion
View Patent ↗A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.
1. A semiconductor memory device, comprising:
an array region comprising a plurality of active regions and a first portion of a first insulating layer disposed between the active regions;
a peripheral region next to the array region, and comprising:
a peripheral structure;
a second insulating layer at a side of the peripheral structure opposite to the array region; and
a second portion of the first insulating layer disposed between the peripheral structure and the second insulating layer, wherein the peripheral structure and the second insulating layer are not in direct contact with each other by being separated by the second portion of the first insulating layer; and
at least a buried word line extending through the active regions and the first portion of the first insulating layer in the array region and the second portion of the first insulating layer, the second insulating layer in the peripheral region, wherein a neck profile portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.
2. The semiconductor memory device according to claim 1 , wherein from the plan view, a first portion of the buried word line through the active regions comprises a first width, a second portion of the buried word line through the peripheral structure comprises a second width, the neck profile portion comprises a third width, wherein the third width is smaller than the first width and the second width.
3. The semiconductor memory device according to claim 2 , wherein the first width and second width are the same.
4. The semiconductor memory device according to claim 2 , further comprising a third insulating layer in the peripheral region and at a side of the second insulating layer opposite to the second portion of the first insulating layer, wherein a fourth portion of the buried word line through the first portion of the first insulating layer comprises a fourth width, a fifth portion of the buried word line through the third insulating layer comprises a fifth width, wherein the fourth width and the fifth width are larger than or equal to the first width and the second width.
5. The semiconductor memory device according to claim 4 , wherein the fourth width and the fifth width are the same.
6. The semiconductor memory device according to claim 4 , wherein the second portion of the first insulating layer and the third insulating layer are not in direct contact with each other by being separated by the second insulating layer.
7. The semiconductor memory device according to claim 4 , wherein the first portion of the first insulating layer, the second portion of the first insulating layer, and the third insulating layer are made of silicon oxide, the second insulating layer is made of silicon nitride.
8. The semiconductor memory device according to claim 1 , wherein from a cross-sectional view, a first portion of the buried word line through the active regions comprises a first thickness, a second portion of the buried word line through the peripheral structure comprises a second thickness, the neck profile portion comprises a third thickness, wherein the third thickness is larger than the first thickness and the second thickness.
9. The semiconductor memory device according to claim 8 , wherein the second thickness is larger than the first thickness.
10. The semiconductor memory device according to claim 8 , wherein a fourth portion of the buried word line through the first portion of the first insulating layer comprises a fourth thickness, the fourth thickness is larger than the first thickness, the second thickness and the third thickness.
11. The semiconductor memory device according to claim 8 , further comprising a third insulating layer in the peripheral region and at a side of the second insulating layer opposite to the second portion of the first insulating layer, wherein a fifth portion of the buried word line through the third insulating layer comprises a fifth thickness, wherein the fifth thickness and the third thickness are the same.
12. The semiconductor memory device according to claim 11 , further comprising an insulating capping layer disposed on the buried word line, wherein a top surface of the insulating capping layer is flush with a top surface of the third insulating layer.
13. The semiconductor memory device according to claim 1 , wherein the second insulating layer comprises a wavy profile from the plan view.