Integrated circuit device with ion doped regions that provide dopant ions to gate dielectric film
An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.
1. An integrated circuit device comprising:
a substrate comprising a plurality of active regions spaced apart from each other;
a device isolation film arranged on the substrate and surrounding the plurality of active regions;
a word line arranged over the plurality of active regions and the device isolation film and extending lengthwise in a first horizontal direction;
a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line;
a first impurity region arranged between the substrate and the gate dielectric film; and
a second impurity region arranged between the device isolation film and the gate dielectric film,
wherein a maximum width of a second portion of the word line is greater than a maximum width of a first portion of the word line in a second horizontal direction that is orthogonal to the first horizontal direction, with each of the first portion and the second portion including an entire vertical thickness of the word line, the first portion being arranged over the plurality of active regions, and the second portion being arranged over the device isolation film, and
wherein a thickness of the second impurity region is smaller than a thickness of the first impurity region.
2. The integrated circuit device of claim 1 ,
wherein the first impurity region comprises an amorphous semiconductor layer comprising dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
3. The integrated circuit device of claim 1 ,
wherein the second impurity region comprises an insulating film comprising dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
4. The integrated circuit device of claim 1 ,
wherein the second impurity region comprises an oxygen-rich silicon oxide film, a silicon oxynitride film, a silicon-rich silicon oxide film, a silicon-rich silicon nitride film, or a combination thereof.
5. The integrated circuit device of claim 1 ,
wherein each of the first impurity region and the second impurity region comprises interstitial oxygen.
6. An integrated circuit device comprising:
a substrate comprising a device isolation trench, which defines a plurality of active regions apart from each other;
a device isolation film formed in the device isolation trench;
a word line trench extending lengthwise in a first horizontal direction across the plurality of active regions and the device isolation film;
a gate dielectric film covering an inner wall of the word line trench;
a word line arranged on the gate dielectric film and partially filling the word line trench;
a first impurity region arranged between the substrate and the gate dielectric film and contacting the gate dielectric film; and
a second impurity region arranged between the device isolation film and the gate dielectric film and contacting the gate dielectric film,
wherein a maximum width of a second portion of the word line is greater than a maximum width of a first portion of the word line in a second horizontal direction that is orthogonal to the first horizontal direction, with each of the first portion and the second portion including an entire vertical thickness of the word line, the first portion being arranged over the plurality of active regions, and the second portion being arranged over the device isolation film, and
wherein a thickness of the second impurity region is smaller than a thickness of the first impurity region.
7. The integrated circuit device of claim 6 , wherein
the first impurity region extends outside the word line trench and along the inner wall of the word line trench, and
the first impurity region comprises dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
8. The integrated circuit device of claim 6 , wherein
the second impurity region extends outside the word line trench and along the inner wall of the word line trench, and
the second impurity region comprises dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
9. The integrated circuit device of claim 6 , wherein
the gate dielectric film comprises an oxygen-rich oxide film.
10. The integrated circuit device of claim 6 ,
wherein the first impurity region and the second impurity region each comprises interstitial oxygen.
11. The integrated circuit device of claim 6 ,
wherein each of the first impurity region and the second impurity region comprises interstitial atoms comprising dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
12. The integrated circuit device of claim 6 ,
wherein the second impurity region comprises an oxygen-rich silicon oxide film, a silicon oxynitride film, or a combination thereof.
13. The integrated circuit device of claim 6 , wherein
the first impurity region extends outside the word line trench and along a portion of the inner wall of the word line trench and is apart from a main surface of the substrate; and
the second impurity region extends outside the word line trench and along an other portion of the inner wall of the word line trench and is apart from the top surface of the device isolation film.
14. The integrated circuit device of claim 6 , further comprising:
an impurity region arranged in a flat plate shape in the substrate and extending parallel to a main surface of the substrate,
wherein the impurity region comprises interstitial atoms comprising oxygen (O) atoms, silicon (Si) atoms, helium (He) atoms, argon (Ar) atoms, fluorine (F) atoms, or a combination thereof.
15. An integrated circuit device comprising:
a substrate comprising a plurality of active regions spaced apart from each other;
a device isolation film arranged on the substrate and surrounding the plurality of active regions;
a word line arranged over the plurality of active regions and the device isolation film and extending lengthwise in a first horizontal direction;
a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line; and
an impurity region arranged on the substrate and the device isolation film and contacting the gate dielectric film,
wherein a maximum width of a second portion of the word line is greater than a maximum width of a first portion of the word line in a second horizontal direction that is orthogonal to the first horizontal direction, with each of the first portion and the second portion including an entire vertical thickness of the word line, the first portion being arranged over the plurality of active regions, and the second portion being arranged over the device isolation film, and
wherein the impurity region comprises a first impurity region contacting the substrate and a second impurity region contacting the device isolation film, and a thickness of the second impurity region is smaller than a thickness of the first impurity region.
16. The integrated circuit device of claim 15 , wherein
the impurity region comprises dopant ions selected from oxygen (O) ions, silicon (Si) ions, helium (He) ions, argon (Ar) ions, fluorine (F) ions, and combinations thereof.
17. The integrated circuit device of claim 15 , wherein
a lower width of the second portion of the word line is greater than an upper width thereof in the second horizontal direction.