Gate formation scheme for nanosheet transistors having different work function metals and different nanosheet width dimensions
Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistors (FET) device on a substrate. The fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet such that an air gap is between the first gate structure and the second gate structure. An etchant is applied to the first gate structure and the second gate structure such that the etchant enters the air gap and etches the first gate structure and the second gate structure from within the air gap.
1. A method of fabricating a semiconductor device, the method comprising:
performing fabrication operations to form a nanosheet field effect transistors (FET) device on a substrate;
wherein the fabrication operations include:
forming a first channel nanosheet;
forming a second channel nanosheet over the first nanosheet;
forming a first gate structure around the first channel nanosheet;
forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure; and
applying an etchant to the first gate structure and the second gate structure, wherein the etchant is configured to enter the air gap and etch the first gate structure and the second gate structure from within the air gap.
2. The method of claim 1 , wherein the first gate structure comprises:
a first region deposited using a conformal deposition process; and
a second region deposited using a non-conformal deposition process.
3. The method of claim 2 , wherein the conformal deposition process comprises an atomic layer deposition process.
4. The method of claim 3 , wherein the non-conformal deposition process comprises a chemical vapor deposition process.
5. The method of claim 2 , wherein the second gate structure comprises:
a third region deposited using the conformal deposition process; and
a fourth region deposited using the non-conformal deposition process.
6. The method of claim 5 , wherein:
the conformal deposition process comprises an atomic layer deposition process; and
the non-conformal deposition process comprises a chemical vapor deposition process.
7. The method of claim 1 , wherein:
the first gate structure and the second gate structure comprise a gate metal having a work function configured for operation in a first type of FET configured to operate based on a first type of majority carrier; and
applying the etchant comprises applying the etchant for a sufficient duration to remove the first gate structure and the second gate structure.
8. The method of claim 7 , wherein the fabrication operations further comprise:
forming a third gate structure around the first channel nanosheet; and
forming a fourth gate structure around the second channel nanosheet;
wherein the third gate structure and the fourth gate structure comprise a gate metal having a work function configured for operation in a second type of FET configured to operate based on a second type of majority carrier.
9. A method of fabricating semiconductor devices, the method comprising:
performing fabrication operations to form nanosheet field effect transistor (FET) devices on a substrate, wherein the fabrication operations include;
in a first region of the substrate:
forming a first channel nanosheet;
forming a second channel nanosheet over the first nanosheet;
forming a first gate structure around the first channel nanosheet; and
forming a second gate structure around the second channel nanosheet, wherein a first air gap is between the first gate structure and the second gate structure;
in a second region of the substrate:
forming a third channel nanosheet;
forming a fourth channel nanosheet over the third nanosheet;
forming a third gate structure around the third channel nanosheet;
forming a fourth gate structure around the fourth channel nanosheet, wherein a second air gap is between the third gate structure and the fourth gate structure; and
applying an etchant to the third gate structure and the fourth gate structure, wherein the etchant is configured to enter the second air gap and etch the third gate structure and the fourth gate structure from within the second air gap.
10. The method of claim 9 , wherein the third gate structure comprises:
a first region deposited using a conformal deposition process; and
a second region deposited using a non-conformal deposition process.
11. The method of claim 10 , wherein the conformal deposition process comprises an atomic layer deposition process.
12. The method of claim 11 , wherein the non-conformal deposition process comprises a chemical vapor deposition process.
13. The method of claim 10 , wherein the fourth gate structure comprises:
a third region deposited using the conformal deposition process; and
a fourth region deposited using the non-conformal deposition process.
14. The method of claim 13 , wherein:
the conformal deposition process comprises an atomic layer deposition process; and
the non-conformal deposition process comprises a chemical vapor deposition process.
15. The method of claim 9 , wherein:
the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure comprise a gate metal having a work function configured for operation in a first type of FET configured to operate based on a first type of majority carrier; and
applying the etchant comprises applying the etchant for a sufficient duration to remove the third gate structure and the fourth gate structure.
16. The method of claim 15 , wherein the fabrication operations further comprise:
forming a fifth gate structure around the third channel nanosheet; and
forming a sixth gate structure around the fourth channel nanosheet;
wherein the fifth gate structure and the sixth gate structure comprise a gate metal having a work function configured for operation in a second type of FET configured to operate based on a second type of majority carrier.