Gate structures for semiconductor devices
A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. The first gate structure includes a nWFM layer disposed on the first nanostructured channel region, a barrier layer disposed on the nWFM layer, a first pWFM layer disposed on the barrier layer, and a first gate fill layer disposed on the first pWFM layer. Sidewalls of the first gate fill layer are in physical contact with the barrier layer. The second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pWFM layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pWFM layer. Sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.
1 . A semiconductor device, comprising:
a substrate;
a source/drain region disposed on the substrate; and
a gate structure, disposed adjacent to the source/drain region, comprising:
a gate dielectric layer;
an n-type work function metal layer disposed on the gate dielectric layer;
a barrier layer disposed on the n-type work function metal layer;
a p-type work function metal layer comprising a bottom metal portion and a sidewall metal portion disposed on the barrier layer; and
a metal layer comprising a lower metal portion and an upper metal portion, wherein the lower metal portion is in contact with the sidewall metal portion and the upper metal portion is in contact with the barrier layer.
2 . The semiconductor device of claim 1 , wherein the lower metal portion comprises sloped sidewalls, and
wherein the upper metal portion comprises vertical sidewalls.
3 . The semiconductor device of claim 1 , wherein the sidewall metal portion comprises a tapered cross-sectional profile along a first plane and a rectangular cross-sectional profile along a second plane perpendicular to the first plane.
4 . The semiconductor device of claim 1 , wherein the sidewall metal portion comprises a vertical surface facing the barrier layer and a sloped surface facing the metal layer.
5 . The semiconductor device of claim 1 , wherein the barrier layer comprises:
a first layer comprising a metal; and
a second layer comprising an oxide of the metal.
6 . The semiconductor device of claim 1 , wherein the barrier layer comprises:
a first layer comprising a semiconductor material; and
a second layer comprising an oxide of the semiconductor material.
7 . The semiconductor device of claim 1 , wherein the barrier layer comprises a semiconductor layer or a metal layer.
8 . The semiconductor device of claim 1 , wherein the n-type work function metal layer, the p-type work function metal layer, and the metal layer comprise materials different from each other.
9 . The semiconductor device of claim 1 , wherein the p-type work function metal layer comprises an aluminum-free layer.
10 . The semiconductor device of claim 1 , further comprising a nitride layer disposed between the n-type work function metal layer and the barrier layer.
11 . A semiconductor device, comprising:
a substrate;
a first gate structure, disposed on the substrate, comprising:
a first gate dielectric layer,
a barrier layer disposed on the first gate dielectric layer,
a first glue layer comprising a first aluminum-free layer disposed on the barrier layer; and
a first metal layer comprising a first lower portion and a first upper portion, wherein the first lower portion is in contact with the first glue layer and the first upper portion is in contact with the barrier layer; and
a second gate structure, disposed on the substrate, comprising:
a second gate dielectric layer;
a second glue layer comprising a second aluminum-free layer disposed on and in contact with the second gate dielectric layer; and
a second metal layer comprising a second lower portion and a second upper portion, wherein the second lower portion is in contact with the second glue layer and the second upper portion is in contact with the second gate dielectric layer.
12 . The semiconductor device of claim 11 , further comprising a gate spacer disposed along a sidewall of the first gate structure, wherein a bottom surface of the gate spacer is disposed at a plane lower than a bottom surface of the first glue layer.
13 . The semiconductor device of claim 11 , further comprising a gate spacer disposed along a sidewall of the second gate structure, wherein a bottom surface of the gate spacer is disposed at a plane higher than a bottom surface of the second glue layer.
14 . The semiconductor device of claim 11 , wherein the first glue layer comprises a vertical surface facing the barrier layer and a sloped surface facing the first metal layer.
15 . The semiconductor device of claim 11 , wherein the barrier layer comprises a semiconductor layer or a metal layer.
16 . The semiconductor device of claim 11 , wherein the barrier layer comprises:
a first layer comprising a semiconductor material; and
a second layer comprising an oxide of the semiconductor material.
17 . A method, comprising:
forming a gate opening on a substrate;
depositing a first metal layer in the gate opening;
depositing a barrier layer on the first metal layer;
depositing a second metal layer on the barrier layer;
converting a portion of the second metal layer to a metal oxide layer;
removing the metal oxide layer to expose an unconverted portion of the second metal layer; and
depositing a third metal layer on the unconverted portion of the second metal layer.
18 . The method of claim 17 , wherein converting the portion of the second metal layer to the metal oxide layer comprises exposing the second metal layer to oxygen plasma.
19 . The method of claim 17 , wherein depositing the second metal layer comprises depositing an aluminum-free layer.
20 . The method of claim 17 , wherein depositing the barrier layer comprises depositing a semiconductor layer.