Semiconductor devices having low contact resistance and low current leakage
The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.
1. A device, comprising:
a substrate having a surface;
a source region overlying the substrate;
a drain region overlying the substrate;
a channel overlying the substrate and extending between the source region and the drain region, the channel having an upper surface opposite the substrate and including sides orthogonal to the surface of the substrate;
an inverted U-shaped gate structure overlying the substrate and formed around the upper surface and sides of the channel, the inverted U-shaped gate structure including,
a first U-shaped liner on the substrate, the first U-shaped liner being formed from a high-K dielectric material and including sidewalls orthogonal to the surface of the substrate;
a second U-shaped liner formed over the first U-shaped liner, the second U-shaped liner being formed from a work function metal material and including a lower surface proximate the substrate and sidewalls orthogonal to the surface of the substrate; and
a first tungsten fill over the lower surface and sidewalls of the second U-shaped liner;
a first electrical contact connected to the first tungsten fill of the gate structure, the first electrical contact including:
a tungsten contact member selectively deposited, overlying and in direct contact with the first tungsten fill; and
a first copper portion overlying the tungsten contact member; and
a second electrical contact connected to the source region, the second electrical contact including:
a titanium nitride liner overlying the source region;
a second tungsten portion overlying the titanium nitride liner; and
a second copper portion overlying the second tungsten portion.
2. The device of claim 1 , wherein the device is a FinFET transistor.
3. The device of claim 1 , wherein the first electrical contact further includes a diffusion barrier liner overlying the tungsten contact member.
4. The device of claim 1 , wherein the second electrical contact further includes a diffusion barrier liner overlying the second tungsten portion.
5. A device, comprising:
a transistor, having
a source region of a silicon substrate;
a drain region of the silicon substrate;
a channel extending between the source region and the drain region;
a gate structure configured to control current flow in the channel in response to an applied voltage, the gate structure including,
first and second U-shaped liners formed from a high-K dielectric material and a work-function metal, respectively;
a gate electrode formed on the work-function metal, the gate electrode wrapping around the channel;
a first electrical contact connected to the gate electrode; and
a second electrical contact connected to either the source region or the drain region, the first and second electrical contacts each having a lower portion and an upper portion made of two distinct non-alloy metals.
6. The device of claim 5 , further comprising a first diffusion barrier lining the upper portion of the first electrical contact.
7. The device of claim 5 , further comprising a second diffusion barrier lining the upper portion of the second electrical contact.
8. The device of claim 5 , further comprising a third diffusion barrier lining the lower portion of the second electrical contact.
9. The device of claim 8 , wherein the third diffusion barrier is made of titanium nitride (TiN).
10. The device of claim 5 wherein the upper portion is made of copper and the lower portion includes one or more of tungsten, titanium, and aluminum.
11. The device of claim 5 wherein the transistor is a FinFET.
12. The device of claim 5 wherein the gate is a metal gate.
13. The device of claim 12 wherein the metal gate includes an outer layer made of a workfunction metal.
14. The device of claim 5 , further comprising sidewall spacers adjacent to the gate.
15. The device of claim 14 , further comprising a cap over the gate.
16. The device of claim 15 wherein the sidewall spacers and the cap are made of silicon nitride.
17. A device, comprising:
a FinFET on a semiconductor substrate, the FinFET having
a source region formed over the semiconductor substrate;
a drain region formed over the semiconductor substrate;
a channel region extending between the source and drain regions; and
a gate structure configured to control current flow in the channel when a voltage is applied to the gate conductor, the gate structure including,
a gate conductor overlying the substrate and formed around the channel region;
a first U-shaped liner on the substrate, the first U-shaped liner being a high-K dielectric material and including sidewalls extending orthogonal to a surface of the substrate;
a second U-shaped liner over the first U-shaped liner, the second U-shaped liner formed from a work function metal material and including a recess having a lower surface proximate the substrate and sidewalls extending on the sidewalls of the first U-shaped liner; and
a first tungsten fill region formed in the recess of the second U-shaped liner; and
electrical contacts to the source region, the drain region, and the first tungsten fill region of the gate conductor, each electrical contact including a lower layer made of tungsten and an upper layer made of copper.
18. The device of claim 17 wherein the source and drain regions are raised by epitaxial growth.
19. The device of claim 17 wherein elements of the FinFET have dimensions less than 10 nm.