IP Library Granted Patent US 10,490,625
Granted Patent B2
US 10,490,625 · App. 15/941,752 · Granted Nov 26, 2019

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

Inventors: Shin'ichi Nakamata (Matsumoto, JP); Takashi Shiigi (Matsumoto, JP); Yasuyuki Hoshi (Matsumoto, JP); Yuichi Harada (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/063H01L21/046H01L29/1095H01L29/1608H01L29/66068H01L29/7811
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Quick Facts
Patent No.
US 10,490,625
App. No.
15/941,752
Granted
Nov 26, 2019
Kind
B2
Abstract

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.

Claims (42)

1. A silicon carbide semiconductor device having an active region in which a main current flows, comprising:

a silicon carbide semiconductor substrate of a first conductivity type;

a first semiconductor layer of the first conductivity type provided on a front surface of the silicon carbide semiconductor substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the silicon carbide semiconductor substrate;

a first semiconductor region of a second conductivity type selectively provided in a surface of the first semiconductor layer;

a second semiconductor layer provided on the surface of the first semiconductor layer and a surface of the first semiconductor region;

a first semiconductor sub-region of the second conductivity type provided in the second semiconductor layer;

a second semiconductor sub-region of the first conductivity type selectively provided on the first semiconductor layer, in the second semiconductor layer;

third semiconductor sub-regions of the first conductivity type selectively provided in the second semiconductor layer;

a fourth semiconductor sub-region of the second conductivity type provided between two of the third semiconductor sub-regions in the second semiconductor layer, an impurity concentration of the fourth semiconductor sub-region being higher than an impurity concentration of the first semiconductor sub-region of the second semiconductor layer;

a fifth semiconductor sub-region of the second conductivity type provided in the second semiconductor layer at a corner part of an active region in a plan view of the device, the fifth semiconductor sub-region being free of contact with the third semiconductor regions;

a first electrode electrically connected to the third semiconductor sub-regions and the fourth semiconductor sub-region;

a gate insulating film provided on an area of a surface of the second semiconductor layer in which two of the third semiconductor sub-regions sandwich the second semiconductor sub-region;

a gate electrode provided on the gate insulating film; and

a second electrode provided on a rear surface of the silicon carbide semiconductor substrate, wherein

the impurity concentration of the first semiconductor sub-region of the second semiconductor layer is at most 5×10 16 /cm 3 , and

an impurity concentration of the fifth semiconductor sub-region is higher than the impurity concentration of the first semiconductor sub-region of the second semiconductor layer.

2. The silicon carbide semiconductor device according to claim 1 , further comprising

a sixth semiconductor sub-region in contact with a part of the fifth semiconductor sub-region, the part of the fifth semiconductor sub-region facing toward an edge termination region that surrounds a periphery of the active region.

3. The silicon carbide semiconductor device according to claim 1 , wherein

the fifth semiconductor sub-region is in contact with the fourth semiconductor sub-region, at the corner part of the active region.

4. The silicon carbide semiconductor device according to claim 1 , wherein

the gate insulating film is provided on a surface of the fourth semiconductor sub-region, at the corner part of the active region.

5. The silicon carbide semiconductor device according to claim 1 , wherein

the gate electrode is insulated from the second semiconductor layer and the fifth semiconductor sub-region by a field oxide film, at the corner part of the active region.

6. A method of manufacturing a silicon carbide semiconductor device having an active region in which the main current flows, the method comprising:

forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the silicon carbide semiconductor substrate;

selectively forming a first semiconductor region of a second conductivity type in a surface of the first semiconductor layer;

forming a second semiconductor layer of the second conductivity type on the surface of the first semiconductor layer and a surface of the first semiconductor region, an impurity concentration of the second semiconductor layer being at most 5×10 16 /cm 3 ;

selectively forming a second semiconductor sub-region of the first conductivity type on the first semiconductor layer, in the second semiconductor layer, to form a first semiconductor sub-region of the second conductivity type and the second semiconductor sub-region of the first conductivity type in the second semiconductor layer;

selectively forming third semiconductor sub-regions of the first conductivity type in the second semiconductor layer;

forming a fourth semiconductor sub-region of the second conductivity type between the third semiconductor sub-regions in the second semiconductor layer, an impurity concentration of the fourth semiconductor sub-region being higher than an impurity concentration of the first semiconductor sub-region of the second semiconductor layer;

forming a first electrode electrically connected to the third semiconductor sub-regions and the fourth semiconductor sub-region;

forming a gate insulating film on the second semiconductor sub-region;

forming a gate electrode on the gate insulating film; and

forming a second electrode on a rear surface of the silicon carbide semiconductor substrate, wherein

forming the fourth semiconductor sub-region includes forming a fifth semiconductor sub-region of the second conductivity type at a corner part of the active region, the fifth semiconductor sub-region being free of contact with the third semiconductor regions, an impurity concentration of the fifth semiconductor sub-region being higher than the impurity concentration of the first semiconductor sub-region of the second semiconductor layer.

7. The silicon carbide semiconductor device according to claim 1 , wherein

the second semiconductor sub-region is disposed between an adjacent two of the third semiconductor sub-regions, and

the fourth semiconductor sub-region is disposed between another adjacent two of the third semiconductor sub-regions.

8. The method of manufacturing a silicon carbide semiconductor device according to claim 6 , wherein

forming a second semiconductor sub-region includes forming the second semiconductor sub-region to be disposed between an adjacent two of the third semiconductor sub-regions, and

forming a fourth semiconductor sub-region includes forming the fourth semiconductor sub-region to be disposed between another adjacent two of the third semiconductor sub-regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2018
From: NAKAMATA, SHIN'ICHI; SHIIGI, TAKASHI; HOSHI, YASUYUKI; HARADA, YUICHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 045398/0410 →
Priority Claims (1)
JP 2017-108596 · May 31, 2017 · national
Continuity (1)
Related Publication 20180350900A1 · Dec 6, 2018