Semiconductor device and fabricating method thereof
A semiconductor device includes a fin structure, a channel layer and a gate stack. The channel layer is disposed on sidewalls of the fin structure, wherein the channel layer contains a two-dimensional (2D) material. The gate stack is disposed over the channel layer, wherein the gate stack includes a ferroelectric layer.
1. A semiconductor device comprising:
a fin structure;
a channel layer on sidewalls of the fin structure, wherein the channel layer comprises a two-dimensional material;
a gate stack over the channel layer, wherein the gate stack comprises a ferroelectric layer; and
a passivation layer between the fin structure and the channel layer.
2. The semiconductor device of claim 1 , wherein the two-dimensional material is made of transition metal dichalcogenides (TMDs), metal carbides, or black phosphorus (BP).
3. The semiconductor device of claim 1 , wherein the gate stack further comprises:
a cap layer over the ferroelectric layer; and
a semiconductor gate over the cap layer.
4. The semiconductor device of claim 1 , further comprising an oxide layer between the channel layer and the gate stack.
5. A semiconductor device, comprising:
a fin structure;
an insulating two-dimensional material layer over the fin structure;
a channel layer over the insulating two-dimensional material layer;
a ferroelectric layer over the channel layer; and
source/drain layers in contact with the insulating two-dimensional material layer and the channel layer.
6. The semiconductor device of claim 5 , wherein the source/drain layers are physically isolated from the fin structure.
7. The semiconductor device of claim 5 , wherein the source/drain layers are electrically isolated from the fin structure.
8. The semiconductor device of claim 5 , wherein the insulating two-dimensional material layer comprises boron nitride.
9. The semiconductor device of claim 5 , wherein the source/drain layers are made of metal.
10. A semiconductor device comprising:
a transistor including a fin structure, source and drain layers over the fin structure, an insulating layer between the fin structure and the source and drain layers, a channel layer between the source and drain layers, and a gate stack including:
a ferroelectric layer on the channel layer; and
a gate layer on the ferroelectric layer.
11. The semiconductor device of claim 10 , wherein the channel layer includes a semiconductor two-dimensional (2D) material.
12. The semiconductor device of claim 10 , wherein the channel layer is a conformally deposited channel layer.
13. The semiconductor device of claim 10 , wherein the insulating layer includes an insulator 2D material and the channel layer is between the ferroelectric layer and the insulating layer.
14. The semiconductor device of claim 13 , wherein the insulating layer is a conformally deposited insulating layer.
15. The semiconductor device of claim 13 , wherein the insulating layer includes boron.
16. The semiconductor device of claim 13 , wherein the insulating layer includes nitride.
17. The semiconductor device of claim 10 , wherein the ferroelectric layer is a gate dielectric layer doped with a semiconductor material.
18. The semiconductor device of claim 10 , wherein the ferroelectric layer is a gate dielectric layer doped with metal.
19. The semiconductor device of claim 10 , wherein the ferroelectric layer is an orthorhombic ferroelectric layer.
20. The semiconductor device of claim 10 , wherein the insulating layer is further between the fin structure and the channel layer.