Calibration circuit and calibration apparatus including the same
A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.
1. A system comprising:
a first semiconductor device;
a second semiconductor device;
a third semiconductor device; and
a fourth semiconductor device,
wherein the first semiconductor device to the fourth semiconductor device configured to share a resistor for impedance matching,
wherein first semiconductor device to the fourth semiconductor device are coupled to have a chain shape,
wherein the fourth semiconductor device generates a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the fourth semiconductor device.
2. The semiconductor device according to claim 1 , wherein at least one of the first semiconductor device to the fourth semiconductor device includes a volatile memory and at least one of the first semiconductor device to the fourth semiconductor device includes a non-volatile memory.
3. The semiconductor device according to claim 1 ,
wherein each semiconductor device comprises:
a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, and
a signal generator configured to generate a completion signal when performance is completed.
4. The system according to claim 3 , wherein each semiconductor device further comprises:
a command decoder configured to receive the command signal and decode the command signal into a second calibration enable signal; and
a selector configured to select the first completion signal between the first completion signal and the second calibration enable signal according to a select signal, and provide a driving signal,
wherein the second calibration driver is configured to perform the impedance matching operation according to the driving signal.
5. The system according to claim 1 , wherein the semiconductor devices sequentially perform the impedance matching operation according to the chain shape.
6. A system comprising:
a first semiconductor device to an eighth semiconductor device,
wherein the first semiconductor device to the eighth semiconductor device configured to share a resistor for impedance matching,
wherein first semiconductor device to the eighth semiconductor device are coupled to have a chain shape,
wherein the eighth semiconductor device generate a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the eighth semiconductor device.
7. The system according to claim 6 , wherein each semiconductor device comprises:
a calibration driver configured to perform an impedance matching operation using the resistor for the impedance matching, and
a signal generator configured to generate a completion signal when the performance is completed.
8. The system according to claim 6 , wherein the semiconductor devices sequentially perform the impedance matching operation according to the chain shape.
9. The system according to claim 6 , wherein at least one of the semiconductor devices includes a volatile memory and at least one of other semiconductor devices includes non-volatile memories.
10. A system comprising:
a first semiconductor device to an sixteenth semiconductor device,
wherein the first semiconductor device to the sixteenth semiconductor device configured to share a resistor for impedance matching,
wherein first semiconductor device to the sixteenth semiconductor device are coupled to have a chain shape,
wherein the sixteenth semiconductor device generate a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the sixteenth semiconductor device.
11. The system according to claim 10 , wherein each semiconductor device are configured to sequentially perform the impedance matching operation.
12. The system according to claim 10 , wherein each semiconductor device includes a calibration driver configured to perform an impedance matching operation by using the resistor and a signal generator configured to generate a status signal when the performance is completed.
13. The system according to claim 10 , wherein the semiconductor devices sequentially perform the impedance matching operation according to the chain shape.
14. The system according to claim 10 , wherein at least one of the semiconductor devices includes a volatile memory and at least one of other semiconductor devices includes non-volatile memories.
15. A system comprising:
a first semiconductor device to a thirty-second semiconductor device,
wherein the first semiconductor device to the thirty-second semiconductor device is configured to share a resistor for impedance matching,
wherein first semiconductor device to the thirty-second semiconductor device are coupled to have a chain shape,
wherein the thirty-second semiconductor device generate a completion signal when performance is completed and the first semiconductor device receive the completion signal provided from the thirty-second semiconductor device.
16. The system according to claim 15 , wherein at least one of the semiconductor devices includes a volatile memory and at least one of other semiconductor devices includes non-volatile memories.
17. A system comprising:
a first semiconductor device;
a second semiconductor device;
a third semiconductor device; and
a fourth semiconductor device,
wherein the first semiconductor device to the fourth semiconductor device configured to share a resistor for impedance matching,
wherein first semiconductor device to the fourth semiconductor device are coupled to have a chain shape,
wherein at least one of the first semiconductor device to the fourth semiconductor device includes a volatile memory and at least one of the first semiconductor device to the fourth semiconductor device includes a non-volatile memory.
18. The semiconductor device according to claim 17 , wherein each semiconductor device comprises:
a first calibration driver configured to, based on a first calibration enable signal, perform an impedance matching operation according to the resistor, and
a signal generator configured to generate a completion signal when performance is completed.
19. The system according to claim 18 , wherein each semiconductor device further comprises:
a command decoder configured to receive the command signal and decode the command signal into a second calibration enable signal; and
a selector configured to select the first completion signal between the first completion signal and the second calibration enable signal according to a select signal, and provide a driving signal,
wherein the second calibration driver is configured to perform the impedance matching operation according to the driving signal.
20. The system according to claim 17 , wherein the semiconductor devices sequentially perform the impedance matching operation according to the chain shape.