Semiconductor memory device
A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memory 100 of the disclosure includes a memory cell array 110 and a page buffer/sense circuit 170 . The memory cell array 110 includes a plurality of memory cells. The page buffer/sense circuit 170 holds data read from a page selected by the memory cell array 110 or holds data to be programmed to a page selected by the memory cell array 110 . The page buffer/sense circuit 170 is arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array 110 . n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.
1. A semiconductor storage device, comprising:
a memory cell array, comprising a plurality of memory cells;
a page buffer sense circuit, holding data read from a page selected by the memory cell array or holding data to be programmed to a page selected by the memory cell array,
wherein within one pitch in a row direction defined by p bit lines extending from the memory cell array, the page buffer sense circuit is arranged into n columns×m segments, wherein n is an integer equal to or greater than 2, and m is an integer equal to or greater than 2,
wherein one pitch in the row direction is defined based on a designed number or the pitch of wires of an even bit lines and an odd bit lines in the memory cell array.
2. The semiconductor storage device as claimed in claim 1 , wherein the page buffer sense circuit comprises a latch circuit, and a plurality of wires for n sets of latch circuits are formed within the one pitch.
3. The semiconductor storage device as claimed in claim 2 , wherein a first wire in which a first latch circuit is connected to a first node for holding data is arranged to be different from a second wire in which a second latch circuit is connected to a second node for holding data.
4. The semiconductor storage device as claimed in claim 3 , wherein a third wire connected to a first sense node of a first page buffer sense circuit and a fourth wire connected to a second sense node of a second page buffer sense circuit are formed between the first wire and the second wire.
5. The semiconductor storage device as claimed in claim 4 , wherein a fifth wire connected to ground is formed between the third wire and the fourth wire.
6. The semiconductor storage device as claimed in claim 5 , wherein the first wire and the second wire are arranged to be linearly symmetrical with respect to the fifth wire.
7. The semiconductor storage device as claimed in claim 4 , wherein the first node receives a charge from the first sense node through a first transfer transistor, and the second node receives a charge from the second sense node through a second transfer transistor.
8. The semiconductor storage device as claimed in claim 2 , wherein the n sets of latch circuits are formed in an N-well region and a P-well region defined based on the one pitch.
9. The semiconductor storage device as claimed in claim 8 , wherein P-channel metal-oxide-semiconductor transistors of the n sets of latch circuits are formed in the N-well region, and N-channel metal-oxide-semiconductor transistors of the n sets of latch circuits are formed in the P-well region.
10. The semiconductor storage device as claimed in claim 1 , wherein the page buffer sense circuit is arranged into 2 columns×4 segments in the one pitch.
11. The semiconductor storage device as claimed in claim 10 , wherein within the one pitch and on inner sides of a pair of wires for power supply, a wire connected to a node of a first latch circuit, a wire connected to another node of the first latch circuit, a wire connected to a first sense node, a wire connected to ground, a wire connected to a node of a second latch circuit, and a wire connected to another node of the second latch circuit are sequentially formed.